Patents by Inventor Ying Chang
Ying Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240101784Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.Type: ApplicationFiled: September 5, 2023Publication date: March 28, 2024Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng
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Publication number: 20240107776Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.Type: ApplicationFiled: January 5, 2023Publication date: March 28, 2024Inventors: Chun-Chieh LU, Chih-Yu CHANG, Yu-Chuan SHIH, Huai-Ying HUANG, Yu-Ming LIN
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Patent number: 11943643Abstract: An access point (AP) and a station (STA) communicate with each other, with the AP indicating to the STA either or both of a preamble detection (PD) channel and a signaling (SIG) content channel and with the STA being initially monitoring a primary frequency segment of a plurality of frequency segments in an operating bandwidth of the AP. A downlink (DL) or triggered uplink (UL) communication is performed between the AP and the STA during a transmission opportunity (TXOP) such that: (i) during the TXOP, the STA monitors a preamble on the PD channel and decodes a SIG content on the SIG content channel; and (ii) after an end of the TXOP, the STA switches to the primary frequency segment.Type: GrantFiled: July 21, 2021Date of Patent: March 26, 2024Assignee: MediaTek Singapore Pte. Ltd.Inventors: Kai Ying Lu, Yongho Seok, Hung-Tao Hsieh, Cheng-Yi Chang, James Chih-Shi Yee, Jianhan Liu, Po-Yuen Cheng
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Publication number: 20240096789Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Meng-Sheng CHANG, Chien-Ying CHEN, Yao-Jen YANG
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Publication number: 20240096998Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
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Patent number: 11934065Abstract: A display device includes a substrate, a first light emitting element, a second light emitting element, and an optical film sheet. The first light emitting element and the second light emitting element are disposed on the substrate. The first light emitting element emits a first light, and the first light has a first wavelength range. The second light emitting element emits a second light, and the second light has a second wavelength range. The optical film sheet is disposed above the first light emitting element and the second light emitting element. The optical film sheet includes a first zone and a second zone. The first zone includes a first cholesteric liquid crystal, and the first cholesteric liquid crystal reflects light in at least the first wavelength range. The second zone includes a second cholesteric liquid crystal, and the second cholesteric liquid crystal reflects light in at least the second wavelength range.Type: GrantFiled: June 8, 2023Date of Patent: March 19, 2024Assignee: AUO CorporationInventors: Wan Heng Chang, Min-Hsuan Chiu, Syuan-Ying Lin, Wei-Ming Cheng
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240088225Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Publication number: 20240088327Abstract: A light emitting device includes a light-emitting laminate and an insulating reflective structure. The insulating reflective structure includes n pairs of dielectric layers stacked on the light-emitting laminate. Each of the n pairs of dielectric layers includes a first material layer and a second material layer. The first material layer has a first refractive index, and the second material layer has a second refractive index that is greater than the first refractive index of the first material layer. For each pair of dielectric layers among m1 pairs of dielectric layers out of the n pairs of dielectric layers, the first material layer has an optical thickness that is greater than that of the second material layer, where 0.5n?m1?n, and n and m1 are natural numbers greater than 0.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Shiwei LIU, Jin XU, Baojun SHI, Shuijie WANG, Ke LIU, Chung-ying CHANG
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Publication number: 20240085369Abstract: Disclosed is a self-powered formaldehyde sensing device, comprising: a triboelectric material electrode layer including a first substrate and a first electrode layer formed on the first substrate; a triboelectric material dielectric layer including a second substrate, a second electrode layer formed on the second substrate, a dielectric reacting layer formed on the second electrode layer, and a reaction modification layer formed on the dielectric reacting layer to surface-modify the dielectric reacting layer, the reaction modification layer being a phosphomolybdic acid complex (cPMA) layer, the phosphomolybdic acid complex of the phosphomolybdic acid complex layer being obtained by dissolving 4,4?-bipyridine (BPY) in isopropanol (IPA) and then mixing with phosphomolybdic acid (PMA) solution; an elastic spacer; and an external circuit.Type: ApplicationFiled: December 21, 2022Publication date: March 14, 2024Applicant: National Taiwan University of Science and TechnologyInventors: Chih-Yu Chang, Chun-Yi Ho, Yu-Hsuan Cheng, Ying-Ying Chen
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Patent number: 11929418Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.Type: GrantFiled: November 11, 2021Date of Patent: March 12, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
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Patent number: 11928456Abstract: The present disclosure provides a software upgrade system, which is applicable to at least one autonomous mobile robot installed with software in a data distribution service domain. The at least one autonomous mobile robot publishes a version information about the software to the version synchronization topic and receives other version information from the version synchronization topic. Also, the at least one autonomous mobile robot subscribes to a version synchronization topic, and takes the software of the at least one autonomous mobile robot itself as the latest version by a software update procedure to upload to a software update topic, or downloads the latest version of the software from the software update topic and installs it. The present disclosure provides a software upgrade method and a non-transitory recording medium.Type: GrantFiled: March 16, 2022Date of Patent: March 12, 2024Assignee: ADLINK TECHNOLOGY INC.Inventors: Chen-Ying Kuo, Cheng-Ting Chang, Yi-Chen Liu
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Patent number: 11927512Abstract: The invention provides a method for imaging and thickness determination of coatings on coated contact lenses. The method comprises selectively staining a negatively-charged-groups-containing coating over the lens body of a coated contact lens by immersing the coated contact lens in an aqueous solution comprising a fluorescently-labeled polycationic polymer and having a pH of from about 6.5 to 8.0; orthogonally cutting the selectively-stained coated contact lens; and determining the thickness of the coating on the coated contact lens. In addition, the invention provides a method for selecting a candidate coating material comprising negatively charged groups for applying a coating with a desired thickness onto silicone hydrogel contact lenses and for optimizing a coating process for producing coated silicone hydrogel contact lenses with a desired thickness coating thereon.Type: GrantFiled: November 3, 2020Date of Patent: March 12, 2024Assignee: Alcon Inc.Inventors: Yuan Chang, Ying Zheng, Junhao Ge, Steve Yun Zhang, Karen Belinda Sentell, Jinbo Dou
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Publication number: 20240078362Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Norman CHANG, Hsiming PAN, Jimin WEN, Deqi ZHU, Wenbo XIA, Akhilesh KUMAR, Wen-Tze CHUANG, En-Cih YANG, Karthik SRINIVASAN, Ying-Shiun LI
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Patent number: 11923331Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.Type: GrantFiled: February 25, 2021Date of Patent: March 5, 2024Inventors: Wei-Jhih Mao, Kuei-Sung Chang, Shang-Ying Tsai
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Publication number: 20240074337Abstract: A memory device includes a substrate, a bottom electrode disposed over the substrate, a top electrode disposed over the bottom electrode, and a phase change layer disposed between the top electrode and bottom electrode. The phase change layer includes a GeSbTe material that contains a Ge content of about 20 at % or less, a Sb content of about 30 at % or more, and a Te content of about 40 at % at or more.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hengyuan Lee, Cheng-Chun Chang, Chen-Feng Hsu, Tung-Ying Lee, Xinyu BAO
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Publication number: 20240067746Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.Type: ApplicationFiled: February 28, 2023Publication date: February 29, 2024Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
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Patent number: 11914931Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.Type: GrantFiled: December 30, 2019Date of Patent: February 27, 2024Assignee: ANSYS, INC.Inventors: Akhilesh Kumar, Norman Chang, Hsiming Pan, Jimin Wen, Deqi Zhu, Wenbo Xia, Wen-Tze Chuang, En-Cih Yang, Karthik Srinivasan, Ying-Shiun Li
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Publication number: 20240063342Abstract: A light emitting diode includes a semiconductor structure, a first electrode, and a second electrode. The semiconductor structure has a first surface and a second surface. The semiconductor structure includes an N-type semiconductor layer, an active layer, and a P-type semiconductor layer that includes a P-type contact layer, and a P-type base layer located between the P-type contact layer and the active layer. The active layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The first electrode is located on the second surface of the semiconductor structure, and is electrically connected to the N-type semiconductor layer. The second electrode is located on the second surface of the semiconductor structure, and is electrically connected to the P-type semiconductor layer. A P-type dopant concentration in the P-type contact layer gradually decreases along a direction from the first surface towards the second surface.Type: ApplicationFiled: August 15, 2023Publication date: February 22, 2024Inventors: Miaomin CAI, Sihe CHEN, Yashu ZANG, Chungchieh YANG, Chung-Ying CHANG, Chi-Ming TSAI, Zhuoying JIANG, Yu-Chieh HUANG, Su-Hui LIN
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Patent number: D1019346Type: GrantFiled: October 5, 2021Date of Patent: March 26, 2024Assignee: WISTRON NEWEB CORPORATIONInventors: Pei-Ying Tsai, Feng-Ming Chang