Abstract: The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the pillars to partially or entirely remove the convex surface.

Abstract: The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the pillars to partially or entirely remove the convex surface.

Abstract: The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, an oxide layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The oxide layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.

Abstract: The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, a first dielectric layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The first dielectric layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.

Abstract: The present disclosure provides a memory device and a method of manufacturing the memory device. The memory device includes a semiconductor substrate defined with an active area and including a plurality of fins protruding from the semiconductor substrate and disposed within the active area, wherein each of the plurality of fins has a first planar top surface; a first word line extending into the semiconductor substrate and between an adjacent two of the plurality of fins, wherein the first word line includes an oxide layer conformal to surfaces of the adjacent two of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed over the first conductive member and surrounded by the oxide layer; and an isolation extending into the semiconductor substrate and surrounding the active area.

Abstract: The present disclosure provides a memory device and a method of manufacturing the memory device. The memory device includes a semiconductor substrate defined with an active area and including a plurality of fins protruding from the semiconductor substrate and disposed within the active area, wherein each of the plurality of fins has a first planar top surface; a first word line extending into the semiconductor substrate and between an adjacent two of the plurality of fins, wherein the first word line includes an oxide layer conformal to surfaces of the adjacent two of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed over the first conductive member and surrounded by the oxide layer; and an isolation extending into the semiconductor substrate and surrounding the active area.

Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.

Abstract: A memory device includes a substrate, an oxide layer, and a plurality of spacers. The substrate includes a silicon layer, a nitride layer, and a plurality of isolation trenches. The nitride layer overlies the silicon layer. The plurality of isolation trenches penetrates through the nitride layer and a portion of the silicon layer. The oxide layer fills the plurality of isolation trenches and has a surface that is coplanar with a surface of the nitride layer. The plurality of spacers is encircled in the oxide layer, in which top surfaces of the plurality of spacers are covered by the oxide layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming a first sacrificial layer and a second sacrificial layer; forming a first mask layer and a second mask layer, wherein the first mask layer covers the first sacrificial layer, the second mask layer covers the second sacrificial layer; forming a first width controlling element on a lateral surface of the first mask layer and a second width controlling element on a lateral surface of the second mask layer; removing the first mask layer and the second mask layer; and patterning the metallization layer to form a first word line between the first sacrificial layer and the second sacrificial layer, wherein a dimension of the first word line depends on a dimension of the first width controlling element.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming a first sacrificial layer and a second sacrificial layer; forming a first mask layer and a second mask layer, wherein the first mask layer covers the first sacrificial layer, the second mask layer covers the second sacrificial layer; forming a first width controlling element on a lateral surface of the first mask layer and a second width controlling element on a lateral surface of the second mask layer; removing the first mask layer and the second mask layer; and patterning the metallization layer to form a first word line between the first sacrificial layer and the second sacrificial layer, wherein a dimension of the first word line depends on a dimension of the first width controlling element.

Abstract: A semiconductor memory device manufacturing method includes: sequentially forming a lower oxide layer, a word line metal layer and an upper oxide layer over at least a portion of a memory cell; forming a through hole passing through the upper oxide layer, the word line metal layer and the lower oxide layer to expose the portion of the memory cell; forming a sacrificial pillar into the through hole; removing the upper oxide layer to expose a top portion of the sacrificial pillar; sequentially forming a first oxide spacer sidewall, a nitride spacer sidewall and a second oxide spacer sidewall on a sidewall of the top portion of the sacrificial pillar; removing the nitride spacer sidewall to form a void gap; etching the word line metal layer through the void gap to form separate word lines.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. A substrate is provided. A multi-layer structure is formed over the substrate, wherein the multi-layer structure includes a semiconductive material layer and an oxide layer over the semiconductive material layer. The oxide layer is patterned to form a first patterned layer. A second patterned layer is formed on the semiconductive material layer and alternately arranged with the first patterned layer. A first etching operation is performed on the substrate using a comprehensive pattern of the first patterned layer and the second patterned layer.

Abstract: A method of manufacturing the same is provided. The method includes providing a substrate. The method also includes forming a target layer over the substrate. The method further includes forming a patterned mask structure over the target layer. In addition, the method includes forming an etching stop layer over the patterned mask structure. The method also includes forming an underlayer over the etching stop layer; and performing an etching process to pattern the target layer.

Abstract: A method of manufacturing the same is provided. The method includes providing a substrate. The method also includes forming a target layer over the substrate. The method further includes forming a patterned mask structure over the target layer. In addition, the method includes forming an etching stop layer over the patterned mask structure. The method also includes forming an underlayer over the etching stop layer; and performing an etching process to pattern the target layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first isolation structure, and a second isolation structure. The substrate has a first region and a second region. The first isolation structure is disposed within the first region of the substrate. The first isolation structure includes a first dielectric layer and a first nitridation layer disposed between the substrate and the first dielectric layer. The second isolation structure is disposed within the second region of the substrate.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate. The method also includes forming a first trench within the substrate. The method further includes forming a first nitridation layer within the first trench. In addition, the method includes forming a first isolation layer on the first nitridation layer to form a first isolation structure.