Patents by Inventor Ying-Cheng Chuang
Ying-Cheng Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070063260Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: ApplicationFiled: November 22, 2006Publication date: March 22, 2007Inventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Patent number: 7135731Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.Type: GrantFiled: December 10, 2003Date of Patent: November 14, 2006Assignee: Nanya Technology Corp.Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
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Patent number: 7115477Abstract: A gate with dual gate dielectric layer and fabrication method thereof. A semiconductor substrate is provided, on which a dielectric layer and a patterned hard mask layer with an opening are sequentially formed. A spacer is formed on a sidewall of the opening. The semiconductor substrate is ion implanted, the spacer and the exposed dielectric layer are removed, and a gate oxide layer is formed on the bottom of the opening.Type: GrantFiled: July 2, 2004Date of Patent: October 3, 2006Assignee: Nanya Technology CorporationInventors: Chung-Lin Huang, Ying-Cheng Chuang
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Publication number: 20060088967Abstract: The present invention provides a method of manufacturing a FinFET transistor, comprising the steps of: forming a plurality of trenches in a semiconductor substrate, forming a dielectric layer on the semiconductor substrate and filling the trenches, and etching back the dielectric layer to a level below the surface of the substrate to form one or more semiconductor fins standing between the trenches as an active region, such as a source, drain, and channel for the FinFET transistor.Type: ApplicationFiled: April 26, 2005Publication date: April 27, 2006Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Nan Hsiao, Ying-Cheng Chuang
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Patent number: 7022573Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.Type: GrantFiled: July 2, 2004Date of Patent: April 4, 2006Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
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Publication number: 20060063339Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.Type: ApplicationFiled: November 9, 2005Publication date: March 23, 2006Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang
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Patent number: 7005701Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.Type: GrantFiled: December 13, 2002Date of Patent: February 28, 2006Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Chung-Lin Huang, Ying-Cheng Chuang
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Patent number: 6995061Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.Type: GrantFiled: February 18, 2004Date of Patent: February 7, 2006Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang
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Patent number: 6921694Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.Type: GrantFiled: May 19, 2003Date of Patent: July 26, 2005Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Patent number: 6916715Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.Type: GrantFiled: October 27, 2003Date of Patent: July 12, 2005Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Chung-Lin Huang, Ying-Cheng Chuang
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Publication number: 20050127422Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
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Patent number: 6893919Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.Type: GrantFiled: March 26, 2004Date of Patent: May 17, 2005Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang
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Publication number: 20050101090Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.Type: ApplicationFiled: December 15, 2004Publication date: May 12, 2005Inventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Publication number: 20050087823Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.Type: ApplicationFiled: November 19, 2004Publication date: April 28, 2005Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Nan Hsiao, Chao-Sung Lai, Yung-Meng Huang, Ying-Cheng Chuang
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Patent number: 6872623Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: GrantFiled: March 24, 2003Date of Patent: March 29, 2005Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Patent number: 6870216Abstract: A stacked gate vertical flash memory and a fabrication method thereof. The stacked gate vertical flash memory comprises a semiconductor substrate with a trench, a source conducting layer formed on the bottom of the trench, an insulating layer formed on the source conducting layer, a gate dielectric layer formed on a sidewall of the trench, a conducting spacer covering the gate dielectric layer as a floating gate, an inter-gate dielectric layer covering the conducting spacer, and a control gate conducting layer filled in the trench.Type: GrantFiled: June 26, 2003Date of Patent: March 22, 2005Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chi-Hui Lin
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Patent number: 6855966Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.Type: GrantFiled: May 9, 2003Date of Patent: February 15, 2005Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang
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Patent number: 6847068Abstract: A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.Type: GrantFiled: May 19, 2003Date of Patent: January 25, 2005Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Publication number: 20040262673Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.Type: ApplicationFiled: March 16, 2004Publication date: December 30, 2004Inventors: Ching-Nan Hsiao, Chao-Sung Lai, Yung-Meng Huang, Ying-Cheng Chuang
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Publication number: 20040266108Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.Type: ApplicationFiled: February 18, 2004Publication date: December 30, 2004Inventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang