Patents by Inventor Ying-Cheng Chuang
Ying-Cheng Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140252532Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
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Patent number: 8658538Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.Type: GrantFiled: March 7, 2013Date of Patent: February 25, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8647988Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: March 4, 2013Date of Patent: February 11, 2014Assignee: Nanya Technology CorporationInventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8426925Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.Type: GrantFiled: November 12, 2010Date of Patent: April 23, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8415728Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: GrantFiled: November 12, 2010Date of Patent: April 9, 2013Assignee: Nanya Technology Corp.Inventors: Ying Cheng Chuang, Ping Cheng Hsu, Sheng Wei Yang, Ming Cheng Chang, Hung Ming Tsai
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Patent number: 8334196Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.Type: GrantFiled: November 1, 2010Date of Patent: December 18, 2012Assignee: Micron Technology, Inc.Inventors: Ying-Cheng Chuang, Hung-Ming Tsai, Sheng-Wei Yang, Ping-Cheng Hsu, Ming-Cheng Chang
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Publication number: 20120119276Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
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Publication number: 20120119277Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: NANYA TECHNOLOGY CORP.Inventors: YING CHENG CHUANG, PING CHENG HSU, SHENG WEI YANG, MING CHENG CHANG, HUNG MING TSAI
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Publication number: 20120108047Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.Type: ApplicationFiled: November 1, 2010Publication date: May 3, 2012Inventors: Ying-Cheng Chuang, Hung-Ming Tsai, Sheng-Wei Yang, Ping-Cheng Hsu, Ming-Cheng Chang
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Patent number: 7714445Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.Type: GrantFiled: December 5, 2007Date of Patent: May 11, 2010Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chung-Lin Huang, Shih-Yang Chiu
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Patent number: 7700991Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.Type: GrantFiled: November 29, 2007Date of Patent: April 20, 2010Assignee: Nanya Technology Corp.Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chung-Lin Huang, Shih-Yang Chiu
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Patent number: 7576381Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.Type: GrantFiled: December 13, 2007Date of Patent: August 18, 2009Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chung-Lin Huang, Shih-Yang Chiu
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Publication number: 20090124085Abstract: The present invention discloses a method for forming a semiconductor device. The method includes providing a substrate; forming at least one first opening in the substrate to a predetermined depth and exposing a sidewall of the substrate in the first opening; forming a spacer on the sidewall and exposing a portion of the substrate in the bottom of the first opening; etching the exposed substrate in the bottom of the first opening by using the spacer as a mask to form a second opening; forming an isolation layer in the second opening and a portion of the first opening; forming a gate dielectric layer on the surface of the substrate; and forming a conductive layer covering the substrate.Type: ApplicationFiled: January 24, 2008Publication date: May 14, 2009Applicant: NANYA TECHNOLOGY CORP.Inventors: Hung-Ming TSAI, Ying Cheng CHUANG
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Publication number: 20090014886Abstract: The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.Type: ApplicationFiled: December 5, 2007Publication date: January 15, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chung-Lin Huang, Shih-Yang Chiu
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Publication number: 20090014773Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.Type: ApplicationFiled: November 29, 2007Publication date: January 15, 2009Inventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chung-Lin Huang, Shih-Yang Chiu
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Patent number: 7476929Abstract: The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.Type: GrantFiled: November 9, 2005Date of Patent: January 13, 2009Assignee: Nanya Technology CorporationInventors: Ching-Nan Hsiao, Chi-Hui Lin, Ying-Cheng Chuang
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Publication number: 20080283895Abstract: A memory structure including a substrate, dielectric patterns, spacer patterns, a first dielectric layer, a conductor pattern, a second dielectric layer and doped regions is described. The dielectric patterns are disposed on the substrate. The spacer patterns are disposed on each sidewall of each of the dielectric patterns respectively. The first dielectric layer is disposed between the spacer patterns and the substrate. The conductor pattern is disposed on the substrate and covers the spacer patterns. The second dielectric layer is disposed between the spacer patterns and the conductor pattern. The doped regions are disposed in the substrate under each of the dielectric patterns respectively.Type: ApplicationFiled: December 11, 2007Publication date: November 20, 2008Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Nan Hsiao, Ying-Cheng Chuang
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Publication number: 20080265302Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.Type: ApplicationFiled: December 13, 2007Publication date: October 30, 2008Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Nan Hsiao, Ying-Cheng Chuang, Chung-Lin Huang, Shih-Yang Chiu
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Patent number: 7323743Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: GrantFiled: November 22, 2006Date of Patent: January 29, 2008Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin
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Patent number: 7205603Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.Type: GrantFiled: January 23, 2004Date of Patent: April 17, 2007Assignee: Nanya Technology CorporationInventors: Ying-Cheng Chuang, Chung-Lin Huang, Chi-Hui Lin