Abstract: A power driving chip and method are disclosed. The power driving chip includes an integrated power module disposed in a package structure and including a transistor and a gate driver electrically connected to the transistor; a controller disposed in the package structure and electrically connected to the integrated power module; and a multi-level over-temperature protection circuit for measuring an inner temperature of the integrated power module. When the inner temperature exceeds a first trigger temperature, the multi-level over-temperature protection circuit triggers the controller to reduce the output power of the integrated power module. When the inner temperature exceeds a second trigger temperature, the multi-level overheating protection circuit triggers the controller to turn off the integrated power module. The second trigger temperature is higher than the first trigger temperature.

Abstract: A method for profit sharing is provided. The method includes deciding a first sharing rate according to a first event information and a first category information; obtaining a first sharing amount according to the first sharing rate and a first shared profit of the first category information; deciding a second sharing rate according to a second event information and a second category information; obtaining a second sharing amount according to the second sharing rate and a second shared profit of the second category information; deciding a total sharing amount by summing up the first sharing amount and the second sharing amount; and returning the total sharing amount in response to receiving a request from a user device.

Abstract: The compounds represented by Formula (I), which are peripheral alkyl and alkenyl chains extended benzene derivatives, are useful as dual autotaxin (ATX)/histone deacetylase (HD AC) inhibitors. These compounds may be included in a pharmaceutical composition along with a pharmaceutically acceptable carrier, and be used in a therapeutically effective amount for prophylaxis or treatment of various diseases and disorders.

Abstract: A vapor chamber device has a housing and multiple chambers. The housing includes two shells opposite to each other. The chambers are formed between the two shells. Each chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. Since the chambers are independent from one another, when the vapor chamber device is vertically mounted to a heat source, the chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the vapor chamber device may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.

Abstract: A balance mechanism comprises a working device, a connecting arm assembly having a variable length, a torque-balancing assembly, a weighting member, and a connecting member. The connecting arm assembly couples to the working device. The connecting arm assembly is pivoted to the torque-balancing assembly by a pivot. The weighting member couples to the torque-balancing assembly. The connecting member connects the connecting arm assembly and the torque-balancing assembly. As the distance between the working device and the pivot changes, the distance between the weighting member and the pivot changes accordingly, so that a dynamic balance can be achieved.

Abstract: The present disclosure relates to a method for data writing, a device and a storage medium, wherein the method includes acquiring a first data to be written and saving a plurality of sub-blocks of the first data in one or more designated aggregated queue of multiple aggregated queues according to an aggregation strategy; performing, in each designated aggregated queue, data interception on a plurality of sub-blocks in a current queue to obtain a second data to be written; and writing the second data in a storage device. The data distribution written in the storage device becomes more ideal by a multi-queue aggregation, and thus the method for data writing according to the embodiments of the present disclosure can reduce the time consumed in reading the storage device effectively.

Abstract: The present disclosure relates to a data storage device, system, and a data writing method. The device comprises a controller and a plurality of storage blocks, each storage block consisting of an idle storage block and a non-idle storage block, the controller connecting to each storage block respectively, wherein the controller is configured to generate, when receiving a data writing command, a self-adapting adjustment instruction according to a comparison between a storage distribution state of the storage block and a first threshold value to configure the idle-storage block as an SLC block or an XLC block; the storage block is configured to correspondingly adjust the storage distribution state according to the self-adapting adjustment instruction to store written data in the SLC block or the XLC block of the idle storage block.

Abstract: A method for forming a semiconductor memory structure includes forming an isolation structure surrounding an active region in a substrate. The method also includes forming a first trench to separate the active region into a first active region and a second active region. The method also includes forming a bit line over the bottom portion of the first trench. The method also includes forming a word line surrounding the first active region and the second active region and over the bit line. The method also includes self-aligned forming a contact over the first active region and the second active region. The method also includes forming a capacitor over the contact.

Abstract: A method of fabricating a memory device includes forming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: A method of fabricating a memory device includes firming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: The present disclosure relates to a system and method for codebook construction and use thereof in image quality assessment. A codebook including a plurality of code words may be provided. Each one of the plurality of code words may have a reference score relating to image quality. A test image may be acquired. One or more feature vectors may be extracted from the test image based on statistical independence between neighboring divisive normalization transform coefficients of the test image. A score may be generated based on a comparison between the extracted feature vectors of the test image and at least some of the plurality of code words in the codebook and the corresponding reference scores of the code words.

Abstract: A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

Abstract: The present disclosure provides a sustained release formulation of opioid receptor antagonists comprising a sustained release granule comprising at least one of the opioid receptor antagonist, at least one of pharmaceutical acceptable carrier, and a pH-dependent polymer, wherein the sustained release granule is coated with the pH-dependent polymer, and the opioid receptor antagonist is selected from the group consisting of Nalmefene, Naltrexone, or a salt thereof.

Abstract: A method for data processing, comprising updating intermediate storage information according to data to be processed and address information of the data to be processed in a first storage space, until the intermediate storage information has reached a preset size; and performing, in the first storage space, an operation corresponding to the data to be processed using the intermediate storage information, when the intermediate storage information reaches the preset size. By the above method, the computing cost for performing an operation corresponding to the data to be processed in the first storage space can be reduced, the efficiency in performing the corresponding operation can be improved, and with intermediate storage information adapted to the first storage spaces of different sizes, the number of operations on the first storage spaces can be reduced.

Abstract: The present disclosure relates to a method for data writing, a device and a storage medium, wherein the method includes acquiring a first data to be written and saving a plurality of sub-blocks of the first data in one or more designated aggregated queue of multiple aggregated queues according to an aggregation strategy; performing, in each designated aggregated queue, data interception on a plurality of sub-blocks in a current queue to obtain a second data to be written; and writing the second data in a storage device. The data distribution written in the storage device becomes more ideal by a multi-queue aggregation, and thus the method for data writing according to the embodiments of the present disclosure can reduce the time consumed in reading the storage device effectively.

Abstract: The present disclosure relates to a data storage device, system, and a data writing method. The device comprises a controller and a plurality of storage blocks, each storage block consisting of an idle storage block and a non-idle storage block, the controller connecting to each storage block respectively, wherein the controller is configured to generate, when receiving a data writing command, a self-adapting adjustment instruction according to a comparison between a storage distribution state of the storage block and a first threshold value to configure the idle-storage block as an SLC block or an XLC block; the storage block is configured to correspondingly adjust the storage distribution state according to the self-adapting adjustment instruction to store written data in the SLC block or the XLC block of the idle storage block.

Abstract: A balance mechanism comprises a working device, a connecting arm assembly having a variable length, a torque-balancing assembly, a weighting member, and a connecting member. The connecting arm assembly couples to the working device. The connecting arm assembly is pivoted to the torque-balancing assembly by a pivot. The weighting member couples to the torque-balancing assembly. The connecting member connects the connecting arm assembly and the torque-balancing assembly. As the distance between the working device and the pivot changes, the distance between the weighting member and the pivot changes accordingly, so that a dynamic balance can be achieved.

Abstract: A memory system with a shared buffer architecture for multiple decoders reduces transfer latency and power consumption. Such memory system includes a memory device to generate codewords, and a dynamic memory access (DMA) assembly to receive the generated codewords. A first decoding stage of the system comprises a checksum module and a shared memory buffer, including a memory manager and destination ports, that stores and manages codewords received from the DMA assembly. A second decoding stage of the system comprises a bit-flipping (BF) decoder and a min-sum (MS) decoder, each in communication with the shared memory buffer through a respective one of the destination ports. In managing the codewords stored in the shared memory buffer, the memory manager controls assignment including reassignment of the codewords among the destination ports.

Abstract: A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

Abstract: An electrode material for a secondary battery and a secondary battery are provided. The electrode material for the secondary battery includes tin-manganese-nickel-oxide. The secondary battery includes a cathode, an anode, an electrolyte, and a package structure, wherein the anode includes the electrode material for the secondary battery.