Abstract: A process for reducing dishing in damascene structures formed in low k organic dielectrics is described. A key feature is the insertion of a liner layer between the low k dielectric layer and the etch stop layer. The only requirement for the liner material is that it should have different etching characteristics from the etch stop material so that when trenches are etched in the dielectric they extend as far as the etch stop layer, in the normal way. When this is done it is found that dishing, after CMP, is significantly reduced, particularly for trench structures made up of multiple narrow trenches spaced close together.

Abstract: A composite, dual-hardness polishing pad for use in a linear chemical mechanical polishing apparatus and a method for forming the pad are described. In the composite, dual-hardness polishing pad, a pad body is first provided which has a leading edge and a trailing edge for mounting to a linear belt immediately adjacent to a second polishing pad. The pad body is fabricated of a material that has a first hardness, the leading edge contacts an object being polished on the composite polishing pad before the trailing edge when the linear belt turns in a linear polishing process. The composite polishing pad further includes a buffer pad that is adhesively joined to the leading edge of the pad body for contacting the object that is being polished, the buffer pad may be fabricated of a material that has a second hardness which is at least 20% smaller than the first hardness such that impact on the object being polished is minimized during a linear polishing process.

Abstract: A slurry dispensing unit for a chemical mechanical polishing apparatus equipped with multiple slurry dispensing nozzles is disclosed. The slurry dispensing unit is constructed by a dispenser body that has a delivery conduit, a return conduit and a U-shape conduit connected in fluid communication therein between for flowing continuously a slurry solution therethrough and a plurality of nozzles integrally connected to and in fluid communication with a fluid passageway in the delivery conduit for dispensing a slurry solution. The multiple slurry dispensing nozzles may either have a fixed opening or adjustable openings by utilizing a flow control valve at each nozzle opening.

Abstract: The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

Abstract: A process for manufacturing damascene wiring in integrated circuits is described. Trenches in the top most layer are first over-filled with a soft metal (such as copper) and then a relatively thin layer of a hard material such as tantalum, tantalum nitride, titanium, titanium nitride etc is deposited on the copper surface Under a first set of control conditions CMP is then applied for just long enough to selectively remove this hard material layer from peaks in the copper surface while leaving it intact in the valleys. The control conditions for CMP are then adjusted so that CMP can proceed with material at the peaks being removed at a significantly faster rate than in the valleys. Thus, when the point is reached that all copper outside the trenches has been removed, the trenches are found to be just filled with a flat layer that has no dishing.

Abstract: A method is disclosed to improve the reliability of copper damascene interconnects. This is accomplished by performing a two-stage anneal of the copper metal; first, after the deposition of copper in the damascene, and then for the second time, after the removal of excess copper by chemical mechanical polishing.

Abstract: A new method is provided that affects the polishing rate of the surface of a layer of copper, that has been deposited over the surface of a layer of dielectric. Copper damascene structures have been created in the surface of the layer of dielectric, the layer of dielectric also overlies an alignment mark. The surface of the layer of dielectric that is aligned with the alignment mark is provided with dummy damascene structures, assuring equal polishing rates for active damascene structures and the surface region of the layer of dielectric overlying an alignment mark.

Abstract: Within a method for removing from over a substrate a chemical mechanical polish (CMP) residue layer there is first provided a substrate. There is then formed over the substrate: (1) a chemical mechanical polish (CMP) substrate layer having an aperture formed therein; (2) a chemical mechanical polish (CMP) planarized patterned layer formed within the aperture within the chemical mechanical polish (CMP) substrate layer; and (3) a chemical mechanical polish (CMP) residue layer formed upon at least one of the chemical mechanical polish substrate layer and the chemical mechanical polish (CMP) planarized patterned layer, where at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer has a first aqueous contact angle.

Abstract: A method for forming a series of patterned planarized aperture fill layers within a series of apertures within a topographic substrate layer employed within a microelectronics fabrication. There is first provided a topographic substrate layer employed within a microelectronics fabrication, where the topographic substrate layer comprises a series of mesas of substantially equivalent height but of differing widths and the series of mesas is separated by a series of apertures. There is then formed upon the topographic substrate layer a blanket first aperture fill layer. The blanket first aperture fill layer is formed employing a first simultaneous deposition and sputter method.

Abstract: The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

Abstract: The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.

Abstract: A new method is provided for the creation of the trenches or line patterns of damascene structures. Under the first embodiment of the invention, the trenches that are created for the copper interconnect lines are sputter etched as a result of which the corners of the trenches around the top elevation of the trenches are rounded. Under the second embodiment of the invention a disposable hard mask is created over the surface of the dielectric after which the trenches for the interconnect lines are created. The surface of the hard mask layer including the created trenches are rf sputter etched resulting in a sharp reduction of the angle of incidence between sidewalls of the trenches around the perimeter of the trenches and the surface of the layer of dielectric. The barrier and seed layers are deposited over the surface of the disposable hard mask including the created trenches, the deposited copper is polished down to the surface of the dielectric.

Abstract: A method for forming a trench isolation region within a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then formed over the silicon substrate and filling the trench a silicon oxide trench fill layer. There is then thermally oxidized the silicon substrate and the silicon oxide trench fill layer within a thermal oxidation atmosphere to form a densified silicon oxide trench fill layer upon a silicon oxide trench liner layer within an oxidized trench within an oxidized silicon substrate, where the silicon oxide trench liner layer is formed from oxidation of the silicon substrate when forming the oxidized silicon substrate.

Abstract: The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.

Abstract: An apparatus and a method for chemical mechanical polishing a metal on a semiconductor wafer capable of achieving improved pad life are disclosed. In the apparatus, in addition to a first spray nozzle used for spraying a slurry solution onto the top of a polishing pad, a second spray nozzle is provided for mounting juxtaposed to a conditioning pad for dispensing a cleaning solution capable of dissolving polishing debris formed on the polishing pad surface. The apparatus may further include at least one cleaning solution reservoir for storing and delivering a cleaning solution to the second spray nozzle. The method can be advantageously carried out in two-steps during which a first cleaning solution is sprayed onto the pad surface for dissolving the polishing debris, and then a second cleaning solution is sprayed onto the pad surface for removing or flushing away the dissolved debris.

Abstract: Shallow trench isolation in which trenches having varying dimensions have been formed in a hard surface such as silicon nitride can lead to dishing inside the larger trenches. To overcome this, the trenches were first over-filled with a layer of HDPCVD oxide followed by the deposition of a relatively soft dielectric layer, using a conformal deposition method. CMP was then used to remove both the added layer and most of the original HDPCVD oxide, a small thickness of the latter being left in place. Because of the earlier influence of the added layer the resulting surface was planar and a conventional wet or dry etch could be used to remove the remaining oxide, thereby exposing the top surface and fully filling the trenches without any dishing.

Abstract: After the first layer of copper has been deposited and polished (to form the pattern of copper damascene conducting lines) a layer of Ta or TaN/Cu is deposited. Another thin layer of copper is deposited thereby filling existing pores and recesses in the polished copper lines. A second CMP is applied to the surface of the second deposited layer of copper, this second CMP removes the redundant copper from the space where the Inter Metal Dielectric (IMD) layer will be created. Prior to the deposition of the second layer of copper, a (brief) etchback of the (surface of the) first layer of copper can be performed in order to enhance copper surface integrity and thereby improve the deposition of the second layer of copper. A layer of TaN/Ta and a layer of seed copper can be deposited within the openings for the damascene conducting lines prior to the deposition of these lines.

Abstract: A method for forming planarized shallow trench isolation is described. A pad oxide layer is grown over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches are etched through the nitride and pad oxide layers into the semiconductor substrate wherein there are at least one first wide nitride region between two of the trenches and at least one second narrow nitride region between another two of the trenches. A high density plasma oxide layer is deposited over the nitride layer and within the isolation trenches wherein the high density plasma oxide layer fills the isolation trenches and wherein the high density plasma oxide deposits more thickly in the first region over the wide nitride layer and deposits more thinly in the second region over the narrow nitride layer. A photoresist mask is formed over the high density plasma oxide layer.

Abstract: A method for forming within a microelectronics fabrication a dielectric layer formed over, around and between patterned conductor layers. There is first provided a substrate employed within a microelectronics fabrication upon which is formed a patterned conductor layers. There is then formed over the patterned conductor layer a silicon oxide dielectric layer. There is then treated the silicon oxide dielectric layer to an anisotropic sputter etching process to remove silicon oxide dielectric material without re-deposition from the bottom of the gap between lines of the patterned conductor layer and to reform the silicon oxide dielectric layers on the sidewalls of the patterned lines to form spacer layers thereon. Both the silicon oxide dielectric layer deposition process and the sputter etching process may be repeated as desired to form the desired depth of trench and shape of spacer layer. There is then exposed the substrate to a nitrogen plasma.

Abstract: A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then treated the thermal silicon oxide trench liner layer by exposure to a plasma formed from a gas composition which upon plasma activation simultaneously supplies an active nitrogen containing species and an active oxygen containing species to form a plasma treated thermal silicon oxide trench liner layer. There is then formed upon the plasma treated thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material.