Abstract: A method for forming a copper structure with reduced dishing, using a self-aligned copper electroplating process. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer has a trench therein. A barrier layer is formed over the dielectric layer, a seed layer is formed on the barrier layer, and an insulating layer is formed on the seed layer. The insulating layer is patterned so as to expose the seed layer on the bottom and sidewalls of the trench, preferably using the trench photo mask. A copper layer is selectively electroplated onto the exposed seed layer on the bottom and sidewalls of the trench, while the insulating layer prevents copper deposition outside of the trench. The copper layer, the insulating layer, and the seed layer are planarized, stopping at the dielectric layer. Because of the self-aligned copper geometry, the copper suffers reduced dishing.

Abstract: A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48.

Abstract: A method for forming a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a silicon oxide layer, where the silicon oxide layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1. Finally, there is then annealed thermally the substrate within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the silicon oxide layer a densified silicon oxide layer. The densified silicon oxide layer formed employing the method is formed with an unexpectedly low shrinkage.

Abstract: The present invention provides a method of removing an shallow trench isolation (STI) oxide layer 38 from over alignment marks 30. The invention has two major features: (1) A STI photoresist mask 42A that is used to etch Alignment area trenches 34 around alignment marks 30 and to etch STI trenches 35 in device areas 14; and (2) A "reverse tone" STI photoresist mask 42B that is used to remove the isolation oxide 38 from over the alignment marks 30 and from over the active areas 37. The method begins by providing a substrate 10 having a device area 14, an alignment mark trench area 16; and an alignment mark area 18. A polish stop layer 20 22 is formed over the substrate 10. A trench isolation resist layer 42A is used to etch alignment area trenches 34 around the alignment marks 34 and STI trenches 35 in the device areas. A dielectric layer 38 is formed over the substrate.

Abstract: A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

Abstract: A method for filling a trench within a substrate. There is first provided a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a silicon layer. The silicon layer has an aperture formed therein where the silicon layer is formed within the trench. There is then formed upon the silicon layer and filling the aperture a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) method. Finally, the substrate is annealed thermally in an oxygen containing atmosphere to form within the trench an oxidized silicon layer from the silicon layer, where the oxidized silicon layer is contiguous with a densified gap filling silicon oxide trench fill layer simultaneously formed from the gap filling silicon oxide trench fill layer.

Abstract: A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.

Abstract: An improved method for implementing shallow trench isolation in integrated circuits is described. The method begins with the formation of trenches, through patterning and etching. These trenches are then filled with a conformal layer of silicon oxide. This is followed by overcoating with a layer of a hard material such as silicon nitride or boron nitride. Next, chemical-mechanical polishing is used to remove the hard layer everywhere except where it has filled the depressions that overlie the trenches. Then, a non-selective etch is used to remove the remaining hard layer material as well as some of the silicon oxide, so that a planar surface is maintained. Finally, chemical-mechanical polishing is used a second time to remove excess silicon oxide from above the trenches' surface.

Abstract: A method for filling a trench within a substrate. There is first providing a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method. The method employs an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone: TEOS volume ratio of less than about 2:1. Finally, the substrate is annealed thermally within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the gap filling silicon oxide trench fill layer a densified gap filling silicon oxide trench fill layer. Through the method there is formed a densified gap filling silicon oxide trench fill layer with a limited surface sensitivity, a low etch rate and a limited shrinkage.

Abstract: A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48.

Abstract: A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then formed upon the thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material.

Abstract: The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O.sub.3 TEOS layer 50 70 over a trench oxide 40 to protect the trench oxide from excessive subsequent etch steps. The SACVD O.sub.3 TEOS layer has a higher deposition rate over the trench oxide layer 40 than over the surrounding non-trench thermally grown pad oxides. The trench oxide is preferably formed using a process of PECVD, LPTEOS, or O.sub.3 -TEOS. The invention provides two preferred embodiments: (1) a first self aligned sacrificial O.sub.3 TEOS oxide layer 50 deposited before the pad oxide etch and (2) a second self aligned sacrificial O.sub.3 TEOS oxide layer 70 deposited before the sacrificial implant oxide etch. The invention can be applied in a variety of situations where the trench oxide is exposed to damaging etches.

Abstract: An improved method of gap filling shallow trench isolation with ozone-TEOS is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate. A thermal oxide layer is grown within the isolation trenches. A plasma enhanced SiH.sub.4 oxide layer is deposited over the nitride layer and over the thermal oxide layer within the isolation trenches and treated with N.sub.2 plasma. Thereafter, an ozone-TEOS layer is deposited overlying the plasma enhanced SiH.sub.4 oxide layer and filling the isolation trenches. The ozone-TEOS layer and the plasma enhanced SiH.sub.4 oxide layer are polished away stopping at the nitride layer. This completes the formation of shallow trench isolation in the fabrication of the integrated circuit device.

Abstract: A method for forming, without dishing, a planarized aperture fill layer within an aperture within a substrate. There is first provided a substrate having an aperture formed therein. There is then formed upon the substrate and within the aperture a conformal aperture fill layer, where the conformal aperture fill layer is thicker than the depth of the aperture. There is then formed upon the conformal aperture fill layer a conformal polish stop layer having a lower planar region of the conformal polish stop layer where the conformal aperture fill layer is formed within the aperture. The conformal polish stop layer and the conformal aperture fill layer are then planarized through a first chemical mechanical polish (CMP) planarizing method until there is reached the lower planar region of the conformal polish stop layer, while simultaneously forming a patterned polish stop layer and a partially chemical mechanical polish (CMP) planarized aperture fill layer.

Abstract: A method for forming within a trench within a substrate within an integrated circuit a planarized trench fill layer. There is first provided a substrate having a trench formed therein. There is formed upon the substrate at regions other than those within the trench a first integrated circuit layer which has a composition which inhibits formation upon the first integrated circuit layer of a trench fill layer which is subsequently formed upon the substrate and within the trench. There is also formed within the trench but not upon the substrate at regions other than those within the trench a second integrated circuit layer which has a composition which promotes formation within the trench of the trench fill layer which is subsequently formed upon the substrate and within the trench. Finally, there is formed upon the substrate and within the trench the trench fill layer.

Abstract: Novel 1-aryloxy-4-amino-2-butanols of the formulaArO--CH.sub.2 --CHOH--CH.sub.2 --CH.sub.2 --NR.sup.1 R.sup.2wherein Ar is 1-naphthyl, 2-naphthyl, indene-4(or 5-)yl, 3-(or 5-)chloro-2-pyridyl, phenyl, monosubstituted phenyl or di-substituted phenyl, R.sup.1 is lower alkyl, phenyl, phenylalkyl, 2-hydroxymethyl-2-propyl, adamantyl or lower-cycloalkyl, R.sup.2 is hydrogen or lower alkyl, wherein R.sup.1 and R.sup.2 together with the adjacent nitrogen from a heterocyclic residue and the pharmaceutically acceptable acid addition salts thereof having local anesthetic, beta-adrenergic blocking, antihypertensive and antiarrhythmic properties are disclosed. The compounds are prepared by reacting novel 1-aryloxy-4-chloro-2-butanols with amines. Methods for the preparation of the novel 1-aryloxy-4-chloro-2-butanol intermediates are also disclosed.

Abstract: Novel 1-aryloxy-4-amino-2-butanols of the formulaArO--CH.sub.2 --CHOH--CH.sub.2 --CH.sub.2 --NR.sup.1 R.sup.2wherein AR is 1-naphythyl, 2-naphthyl, indene-4(or 5-)yl, 3-(or 5-)chloro-2-pyridyl, phenyl, monosubstituted phenyl or di-substituted phenyl, R.sup.1 is lower alkyl, phenyl, phenylalkyl, 2-hydroxymethyl-2-propyl, adamantyl or lower-cycloalkyl, R.sup.2 is hydrogen or lower alkyl, wherein R.sup.1 and R.sup.2 together with the adjacent nitrogen form a heterocyclic residue and the pharmaceutically acceptable acid addition salts thereof having local anesthetic, beta-adrenergic blocking, antihypertensive and antiarrhythmic properties are disclosed. The compounds are prepared by reacting novel 1-aryloxy-4-chloro-2-butanols with amines. Methods for the preparation of the novel 1-aryloxy-4-chloro-2-butanol intermediates are also disclosed.

Abstract: Novel 1-aryloxy-4-amino-2-butanols of the formulaArO--CH.sub.2 --CHOH--CH.sub.2 --CH.sub.2 --NR.sup.1 R.sup.2wherein Ar is 1-naphthyl, 2-naphthyl, indene-4(or 5-)yl, 3-(or 5-)chloro-2-pyridyl, phenyl, monosubstituted phenyl or di-substituted phenyl, R.sup.1 is lower alkyl, phenyl, phenyl-alkyl, 2-hydroxymethyl-2-propyl, adamantyl or lower-cycloalkyl, R.sup.2 is hydrogen or lower alkyl, wherein R.sup.1 and R.sup.2 together with the adjacent nitrogen form a heterocyclic residue and the pharmaceutically acceptable acid addition salts thereof having local anesthetic, beta-adrenergic blocking, antihypertensive and antiarrhythmic properties are disclosed. The compounds are prepared by reacting novel 1-aryloxy-4-chloro-2-butanols with amines. Methods for the preparation of the novel 1-aryloxy-4-chloro-2-butanol intermediates are also disclosed.

Abstract: Novel 1-aryloxy-4-amino-2-butanols of the formulaArO--CH.sub.2 --CHOH--CH.sub.2 --CH.sub.2 --NR.sup.1 R.sup.2wherein Ar is 1-naphthyl, 2-naphthyl, indene-4(or 5-)yl, 3-(or 5-)chloro-2-pyridyl, phenyl, monosubstituted phenyl or di-substituted phenyl, R.sup.1 is lower alkyl, phenyl, phenylalkyl, 2-hydroxymethyl-2-propyl, adamantyl or lower-cycloalkyl, R.sup.2 is hydrogen or lower alkyl, wherein R.sup.1 and R.sup.2 together with the adjacent nitrogen form a heterocyclic residue and the pharmaceutically acceptable acid addition salts thereof having local anesthetic, beta-adrenergic blocking, antihypertensive and antiarrhythmic properties are disclosed. The compounds are prepared by reacting novel 1-aryloxy-4-chloro-2-butanols with amines. Methods for the preparation of the novel 1-aryloxy-4-chloro-2-butanol intermediates are also disclosed.

Abstract: Novel 1-aryloxy-4-amino-2-butanols of the formulaArO--CH.sub.2 --CHOH--CH.sub.2 --CH.sub.2 --NR.sup.1 R.sup.2wherein Ar is 1-naphthyl, 2-naphthyl, indene-4(or 5-)yl, 3-(or 5-)chloro-2-pyridyl, phenyl, monosubstituted phenyl or di-substituted phenyl, R.sup.1 is lower alkyl, phenyl, phenylalkyl, 2-hydroxymethyl-2-propyl, adamantyl or lower-cycloalkyl, R.sup.2 is hydrogen or lower alkyl, wherein R.sup.1 and R.sup.2 together with the adjacent nitrogen form a heterocyclic residue and the pharmaceutically acceptable acid addition salts thereof having local anesthetic, beta-adrenergic blocking, antihypertensive and antiarrhythmic properties are disclosed. The compounds are prepared by reacting novel 1-aryloxy-4-chloro-2-butanols with amines. Methods for the preparation of the novel 1-aryloxy-4-chloro-2-butanol intermediates are also disclosed.