Patents by Inventor Ying-Ju Chen

Ying-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pillar structure having cavities
    Patent number: 9263354
    Abstract: An apparatus comprises a pillar formed on a top surface of a semiconductor substrate, wherein the pillar comprises a first pillar region, a second pillar region and a first cavity formed between the first pillar region and the second pillar region, and wherein the first cavity is configured to accommodate a probe pin.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Bump Pad Structure
    Publication number: 20160035684
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Application
    Filed: October 15, 2015
    Publication date: February 4, 2016
    Inventors: Hsiu-Ping Wei, Hsien-Wei Chen, Hao-Yi Tsai, Ying-Ju Chen, Yu-Wen Liu
  • Semiconductor devices having guard ring structure and methods of manufacture thereof
    Patent number: 9245842
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a first functional region of an integrated circuit over a workpiece, and forming a second functional region of the integrated circuit over the workpiece. The method includes forming a guard ring around the first functional region of the integrated circuit. The guard ring is formed in a material layer disposed over the first functional region and the second functional region.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Nien-Fang Wu, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices
    Publication number: 20160013124
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.
    Type: Application
    Filed: July 8, 2014
    Publication date: January 14, 2016
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Capacitor in Post-Passivation Structures and Methods of Forming the Same
    Publication number: 20150380351
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Application
    Filed: September 11, 2015
    Publication date: December 31, 2015
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Contact Test Structure and Method
    Publication number: 20150380329
    Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.
    Type: Application
    Filed: September 4, 2015
    Publication date: December 31, 2015
    Inventors: Jie Chen, Hsien-Wei Chen, Tsung-Yuan Yu, Ying-Ju Chen
  • Semiconductor device including an embedded surface mount device and method of forming the same
    Patent number: 9224709
    Abstract: Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen
  • STRUCTURE AND METHOD FOR PACKAGE WARPAGE CONTROL
    Publication number: 20150357302
    Abstract: Presented herein is a package comprising a molding compound layer and an active device in the molding compound layer. A conductive via passes through the molding compound layer and is adjacent to the active device. A passivation layer is disposed on the molding compound layer. An active PPI is disposed on the passivation layer and is electrically connected to the conductive via. A dummy PPI is disposed on the passivation layer and is electrically isolated from the conductive via and the active device.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Note management methods and systems
    Patent number: 9208222
    Abstract: Note management methods and systems are provided. First, inputs are received along a timeline, and at least one note is generated according to the inputs. The at least one note is recorded and arranged along the timeline. In some embodiments, a thumbnail is generated for a respective predefined interval on the timeline according to the at least one note in the respective predefined interval, and the thumbnail of the respective predefined interval is displayed along the timeline.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: December 8, 2015
    Assignee: HTC CORPORATION
    Inventors: David Folchi, Ying-Ju Chen
  • RING STRUCTURES IN DEVICE DIE
    Publication number: 20150348916
    Abstract: A die includes a metal pad, a passivation layer over the metal pad, and a polymer layer over the passivation layer. A metal pillar is over and electrically coupled to the metal pad. A metal ring is coplanar with the metal pillar. The polymer layer includes a portion coplanar with the metal pillar and the metal ring.
    Type: Application
    Filed: August 25, 2014
    Publication date: December 3, 2015
    Inventors: Ying-Ju Chen, Jie Chen, Hsien-Wei Chen
  • METHOD OF FORMING A SEMICONDUCTOR COMPONENT COMPRISING A SECOND PASSIVATION LAYER HAVING A FIRST OPENING EXPOSING A BOND PAD AND A PLURALITY OF SECOND OPENINGS EXPOSING A TOP SURFACE OF AN UNDERLYING FIRST PASSIVATION LAYER
    Publication number: 20150348922
    Abstract: A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • METHOD FOR TREATING CHIKUNGUNYA VIRUS INFECTION
    Publication number: 20150342911
    Abstract: Disclosed herein is a method for the treatment of an infection with, or disease caused by, Chikungunya virus in a subject. The method includes administering to the subject a therapeutically effective amount of suramin as the active agent.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicants: National Defensive Medical Center, Chung Yuan Christian University
    Inventors: Szu-Cheng Kuo, Tzong-Yuan Wu, Chang-Chi Lin, Yu-Ming Wang, Ying-Ju Chen
  • Contact pad for semiconductor devices
    Patent number: 9196529
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Semiconductor package including an embedded surface mount device and method of forming the same
    Patent number: 9196586
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Ming-Yen Chiu, Der-Chyang Yeh
  • WAFER HAVING PAD STRUCTURE
    Publication number: 20150318225
    Abstract: A wafer including a substrate having a plurality of integrated circuits formed above the substrate, and at least one scribe line between two of the integrated circuits. The wafer further includes a plurality of dielectric layers formed in the at least one scribe line having a process control monitor (PCM) pad structure formed therein, the PCM pad structure having: a plurality of metal pads interconnected by a plurality of conductive vias. The PCM pad further includes a plurality of contact bars in contact with a bottom-most metal pad, the contact bars extending substantially vertically from the bottom-most metal pad into the substrate. Additionally, the PCM pad includes an isolation structure substantially surrounding the plurality of contact bars to isolate the PCM pad structure.
    Type: Application
    Filed: July 14, 2015
    Publication date: November 5, 2015
    Inventors: Ying-Ju CHEN, Hsien-Wei CHEN, Hao-Yi TSAI, Mirng-Ji LII
  • Bump pad structure
    Patent number: 9171811
    Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Yu-Wen Liu, Ying-Ju Chen, Hsiu-Ping Wei
  • Hybrid baculovirus having the capability of infecting at least three insect hosts and uses thereof
    Patent number: 9157072
    Abstract: Disclosed herein is an Autographa californica multiple nucleopolyhedrovirus (AcMNPV) based hybrid baculovirus and its uses thereof. The AcMNPV based hybrid baculovirus is capable of infecting different hosts, and comprises Bombyx mori nuclear polyhedrosis virus (BmNPV) genes of lef9, vlf1, p6.9, and vp80; Maruca vitrata multiple nucleopolyhedrovirus (MaviMNPV) genes of lef2, orf1629, and pe38; and AcMNPV/BmNPV/MaviMNPV-hybrid genes of pk1, lef8, DNA pol, GP41, helicase, orf94, VP1054, orf65, lef4, lef5, and orf99. The AcMNPV based hybrid baculovirus is therefore useful as a bio-tool or bio-insecticide for its capability of delivering genes for production or expression of toxic proteins in at least three different insect hosts.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 13, 2015
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Tzong-Yuan Wu, Mean-Shine Chen, Chao-Yi Teng, Ying-Ju Chen
  • METHOD FOR ENHANCING COLLAGEN SECRETION AND PREVENTING CUTANEOUS AGING USING CHENOPODIUM FORMOSANUM EXTRACT
    Publication number: 20150265527
    Abstract: Provided is a method for enhancing collagen secretion and preventing cutaneous aging using Chenopodium formosanum extract. The Chenopodium formosanum extract includes active ingredients that are able to effectively enhance the ability of collagen secretion of dermal fibroblasts as well as prevent the glycation of collagen and resist the damage of ultraviolet light exposure. The preparation of the Chenopodium formosanum extract is environmental friendly and is able to promote the economic value of Chenopodium formosanum; thus, the present invention is suitable for applications in the development of food products, especially beverages, skin care and cosmetic products.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 24, 2015
    Inventors: Hsiang-Ling Su, Chin-Hsiu Yu, Ying-Ju Chen
  • Pillar Structure having Cavities
    Publication number: 20150262895
    Abstract: An apparatus comprises a pillar formed on a top surface of a semiconductor substrate, wherein the pillar comprises a first pillar region, a second pillar region and a first cavity formed between the first pillar region and the second pillar region, and wherein the first cavity is configured to accommodate a probe pin.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9136318
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen