Patents by Inventor Ying-Ju Chen

Ying-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HYBRID BACULOVIRUS HAVING THE CAPABILITY OF INFECTING AT LEAST THREE INSECT HOSTS AND USES THEREOF
    Publication number: 20150252333
    Abstract: Disclosed herein is an Autographa californica multiple nucleopolyhedrovirus (AcMNPV) based hybrid baculovirus and its uses thereof. The AcMNPV based hybrid baculovirus is capable of infecting different hosts, and comprises Bombyx mori nuclear polyhedrosis virus (BmNPV) genes of lef9, vlf1, p6.9, and vp80; Maruca vitrata multiple nucleopolyhedrovirus (MaviMNPV) genes of lef2, orf1629, and pe38; and AcMNPV/BmNPV/MaviMNPV-hybrid genes of pk1, lef8, DNA pol, GP41, helicase, orf94, VP1054, orf65, lef4, lef5, and orf99. The AcMNPV based hybrid baculovirus is therefore useful as a bio-tool or bio-insecticide for its capability of delivering genes for production or expression of toxic proteins in at least three different insect hosts.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 10, 2015
    Applicant: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Tzong-Yuan Wu, Mean-Shine Chen, Chao-Yi Teng, Ying-Ju Chen
  • HYBRID BACULOVIRUS AND USES THEREOF
    Publication number: 20150252332
    Abstract: Disclosed herein is an Autographa californica multiple nucleopolyhedrovirus (AcMNPV) based hybrid baculovirus and its uses thereof. The AcMNPV based hybrid baculovirus is capable of infecting different hosts, and comprises Maruca vitrata multiple nucleopolyhedrovirus (MaviMNPV) genes of lef1, orf1629, pk1, CDS1, CDS2, and lef2; and AcMNPV/MaviMNPV-hybrid genes of egt and orf152. The AcMNPV based hybrid baculovirus is therefore useful as a bio-insecticide by its capability of delivering genes of toxic proteins to be expressed in at least two different insect hosts.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 10, 2015
    Applicant: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Tzong-Yuan Wu, Mean-Shine Chen, Chao-Yi Teng, Ying-Ju Chen, Chung-Hsiung Wang
  • Contact test structure and method
    Patent number: 9129816
    Abstract: A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Tsung-Yuan Yu, Ying-Ju Chen
  • SEMICONDUCTOR DEVICE INCLUDING AN EMBEDDED SURFACE MOUNT DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20150228606
    Abstract: Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating.
    Type: Application
    Filed: February 13, 2014
    Publication date: August 13, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen
  • SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED SURFACE MOUNT DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20150228580
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices.
    Type: Application
    Filed: February 13, 2014
    Publication date: August 13, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Ming-Yen Chiu, Der-Chyang Yeh
  • Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
    Patent number: 9105588
    Abstract: A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: August 11, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Inductor for Post Passivation Interconnect and A Method of Forming
    Publication number: 20150214148
    Abstract: An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
    Type: Application
    Filed: April 6, 2015
    Publication date: July 30, 2015
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • Pad structure having contact bars extending into substrate and wafer having the pad structure
    Patent number: 9093411
    Abstract: A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive visa in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: July 28, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150137349
    Abstract: A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: JIE CHEN, YING-JU CHEN, HSIEN-WEI CHEN, TSUNG-YUAN YU
  • MECHANISMS FOR FORMING POST-PASSIVATION INTERCONNECT STRUCTURE
    Publication number: 20150137352
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ju CHEN, Hsien-Wei CHEN
  • Post Passivation Interconnect Structures and Methods for Forming the Same
    Publication number: 20150130057
    Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventors: Hsien-Wei Chen, Ying-Ju Chen
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150130049
    Abstract: A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed inside the carrier, the pad is configured for receiving a solder bump and is disposed on a surface of the carrier, the via portion is configured for electrically connecting the metallic member and the pad, and the via portion is disposed proximal to an end of the pad. Further, a method of manufacturing a semiconductor device includes providing a carrier, removing a portion of the carrier for forming a via extending a surface of the carrier to an interior of the carrier, filling the via by a conductive material, and disposing the conductive material on the surface of the carrier, wherein the via is disposed proximal to an end portion of the conductive material.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: YING-JU CHEN, HSIEN-WEI CHEN
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150108641
    Abstract: A method of manufacturing a semiconductor device includes providing a carrier including a first layer, a second layer, a first surface of the first layer and a second surface of the second layer, disposing a plurality of solder bumps on the second surface, disposing a molding between the plurality of solder bumps and over the second surface, cutting the first layer to form a first recess in the first layer, wherein the first recess is above a position between at least two of the plurality of solder bumps, and cutting the molding from a bottom surface of the first recess to form a second recess in the molding between the at least two of the plurality of solder bumps.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 23, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: YING-JU CHEN, HSIEN-WEI CHEN
  • Method of making a semiconductor device having a post-passivation interconnect structure
    Patent number: 9006891
    Abstract: A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Liang, Hsien-Wei Chen, Ying-Ju Chen, Tsung-Yuan Yu, Mirng-Ji Lii
  • Inductor for post passivation interconnect
    Patent number: 9000876
    Abstract: An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • Contact Pad for Semiconductor Devices
    Publication number: 20150091191
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Bond pad structure to reduce bond pad corrosion
    Patent number: 8994181
    Abstract: Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
  • Portable electronic apparatus to bypass screen lock mode for electronic notebook and operation method thereof and computer readable media
    Patent number: 8982077
    Abstract: A portable electronic apparatus and an operation method thereof and a computer readable media are provided. The portable electronic apparatus comprises a touch display unit, and an electronic notebook is displayed in the touch display unit. When the touch display enters a power saving mode, and a trigger event is detected, the power saving mode is ended, and the electronic notebook is directly displayed in the touch display unit without displaying a screen lock mode before displaying the electronic notebook.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 17, 2015
    Assignee: HTC Corporation
    Inventors: Ying-Ju Chen, David Folchi
  • Wafer Level Dicing Method
    Publication number: 20150061079
    Abstract: Disclosed herein is a method for dicing a wafer, the method comprising forming a molding compound layer over each of one or more dies disposed on a wafer, the one or more dies separated by scribe lines, the molding compound layer having gaps over the respective scribe lines. The wafer is separated into individual dies along the gaps of the molding compound in the scribe lines. Separating the wafer into individual dies comprises cutting at least a portion of the substrate with a laser. Forming the molding compound layer comprises applying a stencil over the one or more dies and using the stencil to form the molding compound layer.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsia-Wei Chen
  • Reducing delamination between an underfill and a buffer layer in a bond structure
    Patent number: 8963328
    Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Chang-Pin Huang, Tzuan-Horng Liu, Michael Shou-Ming Tong, Ying-Ju Chen, Tung-Liang Shao, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii