Patents by Inventor Ying-Jui Huang

Ying-Jui Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342302
    Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ying-Jui Huang, Chih-Hang Tung, Tung-Liang Shao, Ching-Hua Hsieh, Chien Ling Hwang, Yi-Li Hsiao, Su-Chun Yang
  • Publication number: 20220130794
    Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11217555
    Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11139177
    Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Patent number: 11101232
    Abstract: A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Jui Huang, Chung-Shi Liu, Hsin-Hung Liao, Chien-Ling Hwang
  • Patent number: 11094561
    Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Publication number: 20200303214
    Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • Publication number: 20200303213
    Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling HWANG, Bor-Ping JANG, Chung-Shi LIU, Hsin-Hung LIAO, Ying-Jui HUANG
  • Publication number: 20200227379
    Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.
    Type: Application
    Filed: October 25, 2019
    Publication date: July 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Jui Huang, Ching-Hua Hsieh, Chien-Ling Hwang, Chia-Sheng Huang
  • Patent number: 10679866
    Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ling Hwang, Bor-Ping Jang, Chung-Shi Liu, Hsin-Hung Liao, Ying-Jui Huang
  • Publication number: 20200170136
    Abstract: A moving assistance structure coupled to an end of a component for assisting in pushing the component into a cabinet or pulling the component out of the cabinet includes a mounting member and a driving member. The mounting member is mounted to the component. The driving member is rotationally coupled to the mounting member and includes a first abutting portion and a second abutting portion. The first abutting portion abuts the cabinet when the driving member is rotated along a first direction to push the component into the cabinet. The second abutting portion abuts the cabinet when the driving member is rotated along a second direction opposite to the first direction to pull the component out of the cabinet.
    Type: Application
    Filed: November 24, 2018
    Publication date: May 28, 2020
    Inventor: YING-JUI HUANG
  • Patent number: 10517183
    Abstract: A hold and release device of reduced size allowing the sliding of a server chassis relative to a rack includes a mounting assembly mounted to the server chassis. A fixing member is rotatably coupled to the mounting assembly and comprises a first protrusion to fasten the server chassis to the rack. A latching button is configured to latch the fixing member to the mounting assembly. A guiding member is connected to a button stage receives the latching button and has a sliding tunnel, and a handle slidably coupled to the guiding member is located in the sliding tunnel.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: December 24, 2019
    Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.
    Inventors: Ying-Jui Huang, Chih-Hsuan Lin
  • Publication number: 20190326251
    Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.
    Type: Application
    Filed: February 1, 2019
    Publication date: October 24, 2019
    Inventors: Chen-Hua Yu, Ying-Jui Huang, Chih-Hang Tung, Tung-Liang Shao, Ching-Hua Hsieh, Chien Ling Hwang, Yi-Li Hsiao, Su-Chun Yang
  • Patent number: 10306962
    Abstract: A protective housing includes a housing and a rotating cover mechanism. An opening and a restriction groove are defined in the housing, and the cover mechanism includes a cover body and a latching member rotatably mounted on the cover body. The cover body includes an outer cover and a supporting plate detachably coupled thereto. The latching member includes a handle, a latch between the outer cover and the supporting plate and coupled to the handle, and a mechanical button adjacent to the latch. The latch includes a positioning groove. The partly exposed mechanical button is located between the outer cover and the supporting plate. The handle causes the latch to be received in the restriction groove and the mechanical button is received in the positioning groove to lock the latch.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 4, 2019
    Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.
    Inventor: Ying-Jui Huang
  • Publication number: 20190103375
    Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.
    Type: Application
    Filed: April 30, 2018
    Publication date: April 4, 2019
    Inventors: Ying-Jui Huang, Chien Ling Hwang, Chih-Wei Lin, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20190074259
    Abstract: A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 7, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Jui HUANG, Chung-Shi LIU, Hsin-Hung LIAO, Chien-Ling HWANG
  • Patent number: 10151326
    Abstract: A device for assembling a heat dissipation fan in a computer includes a cage, a handle, and a movable portion. The handle is rotatably fixed on the cage, the handle has a pushing pole and holes are defined at each distal end. The movable portion is movably and elastically connected to the cage. The movable portion includes a plate with a first limit pillar and a second limit pillar spaced from the first limit pillar; and an elastic element abutting the first limit pillar.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: December 11, 2018
    Assignee: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.
    Inventor: Ying-Jui Huang
  • Patent number: 10115690
    Abstract: A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern layer has a plurality of openings spaced apart to each other and through the pattern layer. A plurality of micro pins are respectively formed in the openings. The pattern layer and the release layer are removed to obtain the micro pins. An isolated conductive micro pin for connecting one or more components is also provided.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Jui Huang, Chung-Shi Liu, Hsin-Hung Liao, Chien-Ling Hwang
  • Patent number: 9984960
    Abstract: Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ling Hwang, Ching-Hua Hsieh, Hsin-Hung Liao, Ying-Jui Huang
  • Patent number: 9966357
    Abstract: A method includes moving a first bond head along a first guide apparatus for a first loop. The first guide apparatus is configured in a ring shape. The method also includes picking up a first die using the first bond head during the first loop, and aligning the first die with a first package substrate. The aligning the first die with the first package substrate includes moving the first package substrate in a first direction and a second direction. The first direction and the second direction are contained in a first plane parallel to the first loop. The method further includes placing the first die over the first package substrate during the first loop.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Yi-Li Hsiao