Patents by Inventor Ying Kit Tsui

Ying Kit Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11367731
    Abstract: A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20220128763
    Abstract: A structure includes a first waveguide and a second waveguide. The first waveguide includes a first strip portion and a first tapered tip portion connected to the first strip portion. The second waveguide includes a second strip portion and a second tapered tip portion connected to the second strip portion, wherein the first tapered tip portion of the first waveguide is optically coupled to the second tapered tip portion of the second waveguide, and the first waveguide and the second waveguide are configured to guide a light. In a region where the light is coupled between the first tapered tip portion and the second tapered tip portion, an effective refractive index of the first waveguide with respect to the light is substantially equal to an effective refractive index of the second waveguide with respect to the light.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Chewn-Pu Jou, Felix Ying-Kit Tsui, Stefan Rusu
  • Patent number: 11251314
    Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
  • Publication number: 20210343881
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a substrate comprising sidewalls that define a trench. A capacitor comprising a plurality of conductive layers and a plurality of dielectric layers that define a trench segment is disposed within the trench. A width of the trench segment continuously increases from a front-side surface of the substrate in a direction towards a bottom surface of the trench.
    Type: Application
    Filed: July 8, 2021
    Publication date: November 4, 2021
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Patent number: 11152383
    Abstract: A memory cell may include first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20210313259
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a semiconductor substrate having a first surface and a first optical coupler disposed on the first surface of the semiconductor substrate. The first optical coupler includes a first surface facing away from the first surface of the semiconductor substrate and a first lateral surface connected to the first surface of the first optical coupler. The first surface of the first optical coupler and the first lateral surface of the optical coupler define an angle greater than 90 degrees. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: HAU-YAN LU, FELIX YING-KIT TSUI, JING-HWANG YANG, FENG YUAN
  • Publication number: 20210280591
    Abstract: Various embodiments of the present disclosure are directed towards a memory cell including first and second storage transistors. A first capacitor includes a first capacitor active region disposed within a substrate and a capacitor plate comprised of a first floating gate portion of a floating gate. A second capacitor includes a second capacitor active region disposed within the substrate and a capacitor plate comprised of a second floating gate portion of the floating gate. The first storage transistor includes source/drain regions disposed within a bit line write region and a first gate electrode comprised of a third floating gate portion of the floating gate. The second storage transistor includes source/drain regions disposed within a bit line read region and a second gate electrode comprised of a fourth floating gate portion of the floating gate. The bit line read and write regions are offset from one another by a non-zero distance.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20210280592
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a first well region, second well region, and third well region disposed within a substrate. The second well region is laterally between the first and third well regions. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and laterally extends from the first well region to the third well region. A dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and comprises source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region, is laterally offset from the bit line write region by a non-zero distance, and comprises source/drain regions disposed on the opposite sides of the floating gate.
    Type: Application
    Filed: October 13, 2020
    Publication date: September 9, 2021
    Inventors: Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20210272990
    Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
  • Patent number: 11063157
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Publication number: 20210202761
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Patent number: 11018168
    Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Shun Lo, Felix Ying-Kit Tsui
  • Patent number: 10985240
    Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: April 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Publication number: 20210104598
    Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.
    Type: Application
    Filed: November 25, 2020
    Publication date: April 8, 2021
    Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
  • Patent number: 10971404
    Abstract: A semiconductor device includes a semiconductor substrate, and a first transistor. The first transistor has a first gate on the semiconductor substrate, and a first lightly doped source/drain region within the semiconductor substrate to determine a first channel region beneath the first gate. A doping ratio determined as a concentration of the first lightly doped source/drain region divided by a concentration of the first channel region ranges from 1.0×1013 to 1.0×1017.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chi Chang, Hsin-Li Cheng, Felix Ying-Kit Tsui
  • Patent number: 10964586
    Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui
  • Publication number: 20200395487
    Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.
    Type: Application
    Filed: August 27, 2020
    Publication date: December 17, 2020
    Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
  • Patent number: 10868110
    Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jyun-Ying Lin, Hsin-Li Cheng, Jing-Hwang Yang, Felix Ying-Kit Tsui, Chien-Li Kuo
  • Patent number: 10784276
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Publication number: 20200286987
    Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.
    Type: Application
    Filed: May 12, 2020
    Publication date: September 10, 2020
    Inventors: WEN-SHUN LO, YU-CHI CHANG, FELIX YING-KIT TSUI