Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.

Abstract: A Schottky diode device includes a substrate having a first conductivity type, a first well region having a second conductivity type disposed in the substrate, and a first doped region having the second conductivity type in the first well region, wherein the first doped region includes a first portion and a second portion, and the first portion and the second portion have different doping concentrations. The first portion includes a region having at least four sides, from a top-view perspective, abutting the second portion.

Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, a pair of source/drain regions and a threshold voltage adjusting region. The gate electrode is over the semiconductor substrate. The channel region is between the semiconductor substrate and the gate electrode. The channel region includes a pair of first sides opposing to each other in a channel length direction, and a pair of second sides opposing to each other in a channel width direction. The source/drain regions are adjacent to the pair of first sides of the channel region in the channel length direction. The threshold voltage adjusting region covers the pair of second sides of the channel region in the channel width direction, and exposing the pair of first sides of the channel region in the channel length direction.

Abstract: A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.

Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having a top surface, a first well region of a first conductivity type in the semiconductor substrate, a second well region of a second conductivity type in the semiconductor substrate, laterally surrounding the first well region, and an isolation region in the first well region and the second well region in proximity to the top surface. The first well region includes a first lighter doped region in proximity to the top surface, and a heavier doped region under the first lighter doped region. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Abstract: The present disclosure provides a method of manufacturing a Schottky diode. The method includes: providing a substrate; forming a first well region in the substrate; defining a first portion and a second portion on a surface of the first well region and performing a first ion implantation on the first portion while keeping the second portion from being implanted; forming a first doped region by heating the substrate to cause dopant diffusion between the first portion and the second portion; and forming a metal-containing layer on the first doped region to obtain a Schottky barrier interface.

Abstract: A semiconductor structure includes a substrate having a first region and a second region defined thereon, a first isolation in the first region, a second isolation in the second region, and a region surrounding the first isolation in the substrate. The substrate includes a first material, and the region includes the first material and a second material. The first isolation has a first width, the second isolation has a second width, and the first width is greater than the second width. A bottom and sidewalls of the first isolation are in contact with the region, and a bottom and sidewalls of the second isolation are in contact with the substrate.

Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.

Abstract: In some embodiments, a photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite the first doping type is disposed in the semiconductor substrate on a side of the first well. A first doped buried region having the second doping type is disposed in the semiconductor substrate, where the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having the second doping type is disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, where the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.

Abstract: An integrated circuit includes two or more rows of heating elements, two or more columns of heating elements, and a plurality of sensing circuits. Each sensing circuit is between two adjacent rows of the rows of heating elements and between two adjacent columns of the columns of heating elements, in a same silicon layer as the rows of heating elements and the columns of heating elements, and configured to generate a bio-sensing signal and a temperature-sensing signal.

Abstract: An integrated circuit includes two or more rows of heating elements, two or more columns of heating elements, and a plurality of sensing areas. Each sensing area is between two adjacent rows of the rows of heating elements and between two adjacent columns of the columns of heating elements and includes a bio-sensing device and a temperature-sensing device.

Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

Abstract: An integrated circuit includes an interconnection structure, first and second sensing pixels over the interconnection structure, and an isolation layer over the first and second sensing pixels. Each of the first and second sensing pixels includes a bio-sensing device, a temperature-sensing device, one or more heating elements adjacent to the bio-sensing device and the temperature-sensing device, and a sensing film over the bio-sensing device. The isolation layer includes a first opening configured to expose the sensing film of the first sensing pixel without exposing the sensing film of the second sensing pixel and a second opening configured to expose the sensing film of the second sensing pixel without exposing the sensing film of the first sensing pixel.

Abstract: An integrated circuit includes a plurality of sensing pixels, each sensing pixel including a sensing film portion, a bio-sensing device configured to generate a first signal responsive to an electrical characteristic of the sensing film portion, a first switching device coupled between the bio-sensing device and a first signal path, a temperature-sensing device configured to generate a second signal responsive to a temperature of the sensing film portion, and a second switching device coupled between the temperature-sensing device and a second signal path.

Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.