Patents by Inventor Ying Kit Tsui
Ying Kit Tsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160320335Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.Type: ApplicationFiled: April 29, 2015Publication date: November 3, 2016Inventors: Ta-Chuan LIAO, Chien-Kuo YANG, Yi-Shao LIU, Tung-Tsun CHEN, Chan-Ching LIN, Jui-Cheng HUANG, Felix Ying-Kit TSUI, Jing-Hwang YANG
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Patent number: 9431107Abstract: Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.Type: GrantFiled: December 14, 2012Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
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Patent number: 9384815Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.Type: GrantFiled: October 8, 2013Date of Patent: July 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hsien Chen, Hau-Yan Lu, Liang-Tai Kuo, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20160104660Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.Type: ApplicationFiled: December 8, 2015Publication date: April 14, 2016Inventors: Alexander KALNITSKY, Hsiao-Chin TUAN, Shih-Fen HUANG, Hsin-Li CHENG, Felix Ying-Kit TSUI
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Publication number: 20160074828Abstract: An integrated circuit includes a plurality of sensing pixels. Each sensing pixel of the plurality of sensing pixels includes a sensing film portion, a potential-sensing device configured to generate a first signal responsive to an electrical characteristic of the sensing film portion, a temperature-sensing device configured to generate a second signal responsive to a temperature of the sensing film portion, and one or more heating elements configured to adjust the temperature of the sensing film portion.Type: ApplicationFiled: May 15, 2015Publication date: March 17, 2016Inventors: Tung-Tsun CHEN, Yi-Shao LIU, Jui-Cheng HUANG, Chin-Hua WEN, Felix Ying-Kit TSUI, Yung-Chow PENG
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Patent number: 9257522Abstract: Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.Type: GrantFiled: September 29, 2014Date of Patent: February 9, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Patent number: 9236326Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.Type: GrantFiled: April 25, 2014Date of Patent: January 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Shih-Fen Huang, Hsin-Li Cheng, Felix Ying-Kit Tsui
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Publication number: 20160005751Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.Type: ApplicationFiled: September 15, 2015Publication date: January 7, 2016Inventors: Felix Ying-Kit Tsui, Huang-Wen Tseng
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Patent number: 9178080Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.Type: GrantFiled: November 26, 2012Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alex Kalnitsky, Felix Ying-Kit Tsui, Hsin-Li Cheng, Jing-Hwang Yang, Jyun-Ying Lin
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Publication number: 20150311140Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Alexander KALNITSKY, Hsiao-Chin TUAN, Shih-Fen HUANG, Hsin-Li CHENG, Felix Ying-Kit TSUI
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Patent number: 9159741Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.Type: GrantFiled: November 17, 2014Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chuan Liao, Chien-Kuo Yang, Felix Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko
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Publication number: 20150132905Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.Type: ApplicationFiled: November 17, 2014Publication date: May 14, 2015Inventors: Ta-Chuan Liao, Chien-Kuo Yang, Felix Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko
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Publication number: 20150098266Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hsien CHEN, Hau-Yan LU, Liang-Tai KUO, Chun-Yao KO, Felix Ying-Kit TSUI
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Publication number: 20150016180Abstract: Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.Type: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Patent number: 8890225Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.Type: GrantFiled: October 14, 2011Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chuan Liao, Chien-Kao Yang, Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko
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Patent number: 8848428Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.Type: GrantFiled: July 13, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20140167127Abstract: Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
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Publication number: 20140145299Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a semiconductor substrate having an conductive region with a plurality of trenches formed therein. A first dielectric layer is formed over respective bottom portions and respective sidewall portions of the respective trenches. A first conductive layer is formed in the trench and over the first dielectric layer, wherein the first dielectric layer acts as a first capacitor dielectric between the conductive region and the first conductive layer. A second dielectric layer is formed in the trench and over the first conductive layer. A second conductive layer is formed in the trench and over the second dielectric layer, wherein the second dielectric layer acts as a second capacitor dielectric between the first conductive layer and the second conductive layer. Other embodiments are also disclosed.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Alex Kalnitsky, Felix Ying-Kit Tsui, Hsin-Li Cheng, Jing-Hwang Yang, Jyun-Ying Lin
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Publication number: 20140016399Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20130092991Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Ta-Chuan Liao, Chien-Kuo Yang, Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko