Abstract: Mechanisms are provided for automatically predicting vehicle weight of a moving vehicle. Vehicle operation data is obtained from one or more on-board sensors/systems of the vehicle and features are extracted. The features are filtered based on a required working condition of the vehicle to identify intervals of features having valid feature data to thereby generate a filtered valid data. The filtered valid data is processed by a first artificial intelligence (AI) computer model based on time slices of the filtered valid data to generate a first prediction of vehicle weight, and by a second AI computer model based on buckets of key variables to generate a second prediction of vehicle weight. The first prediction is fused with the second prediction to generate a final prediction of vehicle weight which is output to downstream computing logic.

Abstract: A method for manufacturing a semiconductor device includes forming a metal-including layer over a semiconductor substrate; forming a hydrophobic polymer layer over the metal-including layer; and forming an amphiphilic polymer layer between the metal-including layer and the hydrophobic polymer layer so as to enhance a bonding force therebetween.

Abstract: A method may include executing a baseline classifier on unreviewed transaction features of an unreviewed transaction record to obtain a baseline account identifier, and executing a comparison model on (i) an unreviewed transaction vector of the unreviewed transaction record and (ii) reviewed transaction vectors to obtain comparison scores. The reviewed transaction vectors may correspond to reviewed transaction records each having a user-approved account identifier. The method may further include selecting, using the comparison scores, a reviewed transaction record. The reviewed transaction record may correspond to a comparison score. The comparison score may correspond to a user-approved account identifier of the reviewed transaction record.

Abstract: The invention provides a processor, a method for executing an instruction on a processor and a computer. The processor comprises at least one single-instruction multiple-thread processing units. The single-instruction multiple-thread processing unit includes a plurality of warps for executing an instruction; a shared register group, which includes a plurality of general-purpose registers shared by the plurality of warps; and a predicate base address register, which is configured to: correspond to the plurality of warps; and indicate a base address for a subset of the plurality of general-purpose registers that serves as a predicate register for the warp in the shared register group, wherein: the warp performs a predicated execution for an instruction in view of a predicate value in the subset of the plurality of general-purpose registers that serves as the predicate register for the warp.

Abstract: Methods for scheduling mixed type traffics via multiple Transmission/Reception Points (TRPs) are provided. In embodiments disclosed herein, a base station provides, and a wireless device receives, a scheduling information for scheduling the mixed type traffics with different Quality of Service (QoS) requirements via multiple TRPs. In a non-limiting example, the mixed type traffics include an enhanced Mobile Broadband (eMBB) service and an Ultra-Reliable and Low Latency Communication (URLLC) traffic service, and the scheduling information can be conveyed in a single Downlink Control Information (DCI) or a pair of DCIs. As such, it is possible to enable efficient scheduling of both eMBB traffic and URLLC traffics simultaneously. As a result, it is possible to satisfy a reliability requirement of the URLLC service without sacrificing spectral efficiency and/or throughput of the eMBB service.

Abstract: A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.

Abstract: A monitoring method includes effecting communication of working data associated with normal operations of a communication device at a first frequency channel and transmitting monitoring data associated with monitoring the communication device at a second frequency channel.

Abstract: Method for computing power network scheduling service based on comprehensive weight decision of network performance and the system thereof are provided.

Abstract: A system may automatically conduct hygiene cycles for a confined space such an interior space of a box suitable for storing and/or carrying packaged food. The system may include a hygiene device that can be attached to the box to conduct the hygiene cycles. The system may also automatically collect information related to the hygiene cycles and transmit the collected information to a network.

Abstract: The present disclosure relates to the field of genetic breeding, in particular, to methods and formulations for inducing abortion or deformation of plant seeds by a VvDUF642 gene. The result of the present disclosure shows that the VvDUF642 gene is continuously expressed at a high level in seedless varieties, but there is no significant change in expression in nucleated varieties. After the VvDUF642 gene is transformed into an Arabidopsis, Arabidopsis seeds are deformed. After the VvDUF642 gene is transformed into a tomato, it causes abortion of tomato seeds. The gene or protein can be used for the construction or screening of seed abortion grape varieties.

Abstract: The invention discloses a processor and a method for executing an instruction with a processor. The processor comprises a set of tiny register files, each of which is connected correspondingly to one of the set of register files and is configured to temporarily store the operand and the output result of the instruction executed by the plurality of physical threads; and an operand collector, which is connected to the set of register files and to the set of tiny register files and is configured to read the operand of the instruction executed by the plurality of physical threads from the set of register files and/or from the set of tiny register files and write the output result of the instruction executed by the plurality of physical threads to the set of register files and/or to the set of tiny register files.

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: This application provides an image processing method and apparatus. The method includes acquiring an identity feature of a source image and an initial attribute feature of at least one measure of a target image in response to receiving a face change request; inputting the identity feature and the initial attribute feature of the at least one measure into a face change model; iteratively performing feature fusion on the identity feature and the initial attribute feature of the at least one measure by using the face change model to obtain a fusion feature; and generating a target face change image based on the fusion feature by using the face change model, and outputting the target face change image, a face in the target face change image being fused with an identity feature of the source face and a target attribute feature of the target face.

Abstract: A monoclonal antibody composition comprises a capture antibody AB7G and a detection antibody AB11A2 for using in preparation of a kit for quantitative detection of amyloid in human body fluids, and the antibodies are monoclonal antibodies secreted by cultured hybridoma cells. The kit specifically recognizes an A?42 oligomer, with a linear detection range of 3.9-125 pg/mL, and a lowest detection limit of 7.8 pg/mL. A core technique for kit assembly lies in that the monoclonal antibody AB7G is fixed on a microplate to serve as the capture antibody, and the monoclonal antibody AB11A2 is labeled and then diluted at 1:2000 to serve as the detection antibody. Meanwhile, the present invention relates to heavy and light chain variable region genes of the monoclonal antibodies AB7G and AB11A2 and peptides encoded thereby.

Abstract: In a method of manufacturing a semiconductor device, a fin structure including a lower fin structure and an upper fin structure disposed over the lower fin structure is formed, wherein the upper fin structure includes dielectric layers and multi-film layers alternately stacked, each of the multi-film layers includes a channel layer, a first protection layer and a second protection layer, and the channel layer is between the first protection layer and the second protection layer. A sacrificial gate structure is formed over the upper fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure after forming the sacrificial gate structure over the upper fin structure. The sacrificial gate structure is removed after forming the source/drain epitaxial layer. The dielectric layers are removed after removing the sacrificial gate structure. A gate structure is formed around the multi-film layers.

Abstract: A flexible photovoltaic bracket includes a number of upright columns, a number of cross beams, a load-bearing rope and a module fastener. The cross beam is correspondingly arranged on a top of the upright column. The load-bearing rope is fixedly connected to the cross beam and is extended between adjacent cross beams. The module fastener includes a pressing block, a fastening component and a clamping assembly. The pressing block and the fastening component are rotationally connected. A receiving cavity is formed between the pressing block and the fastening component for clamping and limiting the load-bearing rope. The pressing block includes a horizontal base plate portion and a hook portion configured to contact a photovoltaic module. The clamping assembly passes through the fastening component and the horizontal base plate portion, and is configured to be fixedly connected to a frame of the photovoltaic module.

Abstract: The present disclosure provides a semiconductor structure that includes a substrate having devices formed thereon and an interconnect structure electrically coupling the devices into an integrated circuit; a passivation structure formed on the interconnect structure; and a capacitor embedded in the passivation structure, wherein the capacitor includes first metal-insulator-metal (MIM) stacks inserted in first trenches, and second MIM stacks formed into first pillar structures.

Abstract: The present application provides a signal transmission method based on random unitary coding modulation and cross-domain iterative detection, including random unitary coding modulation at a signal transmitting end and cross-domain iterative detection at a receiving end. The random unitary coding modulation includes random unitary modulation or random unitary precoding, utilizing random unitary transformations to ensure that an equivalent channel matrix satisfies the correct right unitary invariance assumption. The cross-domain iterative detection includes using a cross-domain iterative receiver to receive a signal obtained after the random unitary coding modulation. The random unitary coding modulation ensures that general OAMP/VAMP, UAMP, and MAMP-type receivers achieve Bayesian optimal performance. The cross-domain iterative detection allows, through cross-domain detection, the receiver to utilize ultra-sparse time-domain channels, including low-complexity MAMP, OAMP/VAMP, and UAMP-type receivers.

Abstract: A chip electrical property detection device and a method of manufacturing the same are provided. The chip electrical property detection device includes a circuit control substrate, an electrical detection module and a flexible conductive structure. The circuit control module includes multiple electrical conduction structures. The electrical detection module includes multiple movable carrying substrates, multiple electrical detection structures and multiple electrical connection structures. The movable carrying substrates are separately arranged on the flexible conductive structure. The electrical detection structures are respectively disposed on the movable carrying substrates and electrically connected to the electrical connection structures. The electrical connection structures penetrate the movable carrying substrates and electrically connect to the electrical conduction structures through the flexible conductive structure, respectively.