Patents by Inventor Ying Su

Ying Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250012665
    Abstract: The present disclosure discloses a method for training a gearbox fault diagnosis model, and a gearbox fault diagnosis method. The method includes: acquiring a motor current signal in an electromechanical system where a gearbox is located; calculating, based on the current signal, characteristic values representing complexity and degree of mutation of the current signal; filtering the characteristic values based on a random forest algorithm to generate a sample data set; and training, based on the data set, a deep reinforcement learning network model to generate the fault diagnosis model. By means of the method for training the gearbox fault diagnosis model according to the present disclosure, merely the current signal is acquired, no additional sensor is needed, and the defect of additional hardware in the prior art is overcome.
    Type: Application
    Filed: August 15, 2022
    Publication date: January 9, 2025
    Inventors: Luo WANG, Zubing ZOU, Junqing LI, Youhan DENG, Zufan WANG, Ying SU
  • Publication number: 20240423696
    Abstract: The invention discloses a surgical smoking knife, which includes: a casing with a slide inside; a smoking tube slidably connected to the slide, with one part located inside the casing and the other part located outside the casing; and an electrode knife disposed on the smoking knives. on the pipe; a control circuit board is arranged on the housing; a flexible transmission circuit slat penetrates into the inside of the smoking pipe through a slide, and its two ends are connected to the control circuit board and the electrode knife respectively. The beneficial effect of the present invention is that it can effectively reduce the friction resistance during telescopic adjustment.
    Type: Application
    Filed: June 24, 2024
    Publication date: December 26, 2024
    Applicant: Zhejiang Shuyou Instrument Equipment Co., Ltd.
    Inventors: Tai HAO, Ying SU, Xianfeng ZHOU, Zuokai YIN, Kongpei LU
  • Publication number: 20240386178
    Abstract: A method (of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells) comprises generating the layout diagram including: reusing one amongst predefined parasitic capacitance (PC) descriptions of corresponding predefined cells that are stored within a database, the reusing including: for a candidate cell amongst the layout cells in the layout diagram, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and when a substantial match is found, reusing the PC description of the matching predefined cell by assigning the same to the candidate cell rather than otherwise making a discrete calculation of a corresponding PC description for the candidate cell.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Ke-Ying SU, Ze-Ming WU, Po-Jui LIN
  • Publication number: 20240386181
    Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second active region edges, calculating a gate resistance value based on the location and first and second active region edges, based on the resistance value, modifying the IC layout diagram by changing the location of the gate via along the gate region and/or adding another gate via positioned at another location along the gate region, and storing the modified IC layout diagram in a storage device.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
  • Patent number: 12135930
    Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Ke-Wei Su, Keng-Hua Kuo, Lester Chang
  • Patent number: 12093629
    Abstract: A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells, the method including generating the layout diagram including: for a candidate cell amongst the layout cells in the layout diagram, avoiding a discrete calculation of a corresponding parasitic capacitance (PC) description including, within a database which stores predefined cells and corresponding parasitic capacitance (PC) descriptions thereof, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell; and, when a substantial match is found, assigning the PC description of the matching predefined cell to the candidate cell.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Ze-Ming Wu, Po-Jui Lin
  • Publication number: 20240247526
    Abstract: The instant disclosure provides a gate device and an umbrella sharing system which utilizes the gate device. The gate device includes a base, an actuator, a pair of gate plates, and an identification sensor. The actuator is disposed on a top surface of the base and includes a latch extending downward through the base. The pair of gate plates are disposed on a bottom surface of the base, and each of the gate plates includes a guiding structure and a locking structure. A waiting zone for receiving an umbrella is defined between the two guiding structures. The latch of the actuator is driven to engage with the locking structures to limit the movement of the gate plates. The identification sensor is above the waiting zone and disposed on the base and is configured to identify the identity of an umbrella which enters the waiting zone.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 25, 2024
    Inventors: Chun-Chia SU, Chi-Yao YU, Po-Feng WANG, Po Ying SU, Ting-Yuan CHENG, Hsin-En FANG, ShaoTing YEN, Pin Wei LIAO, An-Li TING, Hsien An WU, Po-Hsun SU
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Publication number: 20240122906
    Abstract: The present disclosure relates to methods of treating melanoma in a patient in need thereof, comprising administering to the subject a therapeutically effective amount of ripretinib or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 18, 2024
    Inventors: Ying Su, Rodrigo Ruiz Soto
  • Patent number: 11958788
    Abstract: The present invention discloses a method of preparing an alkali activation material by using red mud-based wet grinding and carbon sequestration and an application thereof. The preparation method includes: (1) adding water, red mud, a crystalline control agent, and a grinding aid into a wet grinding carbon sequestration apparatus to perform wet grinding, and simultaneously introducing CO2 until a slurry pH reaches 7 to 7.5; and removing wet grinding balls by a sieve to obtain a slurry A; (2) adding carbide slag, water and a water reducer to a wet planetary ball grinder tank for wet grinding, and removing wet grinding balls by a sieve to obtain a slurry B; (3) taking 50 to 80 parts of the slurry A and 20 to 50 parts of the slurry B and mixing them to obtain an alkali activation material.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 16, 2024
    Assignee: Hubei University Of Technology
    Inventors: Xingyang He, Weilong Li, Ying Su, Zhengqi Zheng, Jin Yang, Yingbin Wang, Hongbo Tan, Chenghao Li
  • Publication number: 20240116845
    Abstract: Provided herein are an indene compound, e.g., a compound of Formula (I), and a pharmaceutical composition thereof. Also provided herein is a method of their use for treating, preventing, or ameliorating one or more symptoms of a fibrotic disease.
    Type: Application
    Filed: November 9, 2023
    Publication date: April 11, 2024
    Inventors: Ying Su, Ziwen Chen, Haishan Wang
  • Publication number: 20240111935
    Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.
    Type: Application
    Filed: November 27, 2023
    Publication date: April 4, 2024
    Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
  • Patent number: 11912630
    Abstract: The present invention provides a method of preparing a recycled cementitious material by a phosphogypsum-assisted carbon sequestration pretreatment process. The method includes: (1) placing 100 mass parts of phosphogypsum, 1 to 2 mass parts of grinding aid, 10 to 20 mass parts of sodium-containing alkali component, 150 to 300 mass parts of zirconia balls, and 150 to 300 mass parts of water into a wet grinding tank for wet grinding. After 10 min to 30 min of wet grinding, introducing CO2 at a flow rate of 1.5 to 2.2 mass parts/min to keep a temperature of a wet grinding slurry below 40° C. When the wet grinding slurry reaches pH=10, ending the wet grinding and sieving out a wet grinding slurry; (2) mixing the wet grinding slurry with 700 to 1000 mass parts of slag and 100 to 350 mass parts of water to obtain a recycled cementitious material.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: February 27, 2024
    Assignee: Hubei University Of Technology
    Inventors: Jin Yang, Xiaolei Yu, Xingyang He, Ying Su, Mingchao Zhang, Qiang Zhang, Zhengqi Zheng, Hongbo Tan
  • Patent number: 11907636
    Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang-Yi Chen, Wen-Hsing Hsieh, Wen-Koi Lai, Keng-Hua Kuo, Kuopei Lu, Lester Chang, Ze-Ming Wu
  • Publication number: 20240034785
    Abstract: Provided herein are retinoid X receptor alpha binders that specifically bind to an epitope of a retinoid X receptor alpha, wherein the epitope comprises a phosphorylated serine at position 56 or 70. Also provided herein are retinoid X receptor alpha/polo-like kinase 1 modulators that inhibit the interaction of a polo-like kinase 1 with a retinoid X receptor alpha comprising a phosphorylated serine at position 56 or 70.
    Type: Application
    Filed: December 7, 2020
    Publication date: February 1, 2024
    Inventors: Xiaokun Zhang, Ying Su, Guobin Xie, Yuqi Zhou
  • Patent number: 11860451
    Abstract: Disclosed herein is a cleaning device for orthokeratology lens, comprising a housing, a cap, a gear module, two cleaning shaft, two cleaning head, and a rotating shaft. The housing comprises two orthokeratology lens bases and an opening. The cap is disposed on the opening. The cleaning shaft comprises a first end connecting to the gear module and a second end. The cleaning head is disposed on the second end of the cleaning shaft. The rotating shaft connects to the gear module.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: January 2, 2024
    Assignee: National Taipei University of Technology
    Inventors: Hsu-Wei Fang, Chen-Ying Su, Hsiao-Hung Chiang
  • Patent number: 11842135
    Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Ke-Wei Su, Keng-Hua Kuo, Lester Chang
  • Publication number: 20230382790
    Abstract: The present invention provides a method of preparing a recycled cementitious material by a phosphogypsum-assisted carbon sequestration pretreatment process. The method includes: (1) placing 100 mass parts of phosphogypsum, 1 to 2 mass parts of grinding aid, 10 to 20 mass parts of sodium-containing alkali component, 150 to 300 mass parts of zirconia balls, and 150 to 300 mass parts of water into a wet grinding tank for wet grinding. After 10 min to 30 min of wet grinding, introducing CO2 at a flow rate of 1.5 to 2.2 mass parts/min to keep a temperature of a wet grinding slurry below 40° C. When the wet grinding slurry reaches pH=10, ending the wet grinding and sieving out a wet grinding slurry; (2) mixing the wet grinding slurry with 700 to 1000 mass parts of slag and 100 to 350 mass parts of water to obtain a recycled cementitious material.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 30, 2023
    Applicant: Hubei University Of Technology
    Inventors: Jin YANG, Xiaolei YU, Xingyang HE, Ying SU, Mingchao ZHANG, Qiang ZHANG, Zhengqi ZHENG, Hongbo TAN
  • Patent number: D1013387
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 6, 2024
    Assignee: KOHER (CHINA) INVESTMENT CO. LTD.
    Inventors: Chia Ying Lee, Fei Ying Su, Ji Min Niu, Hui Ren
  • Patent number: D1066582
    Type: Grant
    Filed: September 12, 2023
    Date of Patent: March 11, 2025
    Assignee: KOHLER (CHINA) INVESTMENT CO., LTD.
    Inventors: Chia Ying Lee, Fei Ying Su, Ji Min Niu, Hui Ren