Patents by Inventor Ying Su

Ying Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR TUNING TECHNOLOGY FILES
    Publication number: 20140282342
    Abstract: A method generally comprises arranging a plurality of layer combinations into a plurality of groups such that each of the layer combinations is assigned to at least one group. A shifting analysis is performed on a plurality of benchmark circuits for each of the groups. At least one tuning vector value is calculated based, at least in part, on a plurality of criteria vectors of the benchmark circuits. A shift is applied on each of the groups by the tuning vector value and a technology file, such as a 2.5 dimensional RC techfile, is regenerated.
    Type: Application
    Filed: June 25, 2013
    Publication date: September 18, 2014
    Inventors: Meng-Fan WU, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Parasitic Capacitance Extraction for FinFETs
    Publication number: 20140258962
    Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Ze-Ming Wu, Hsien-Hsin Sean Lee
  • Parasitic capacitance extraction for FinFETs
    Patent number: 8826213
    Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Ze-Ming Wu, Hsien-Hsin Sean Lee
  • Methods and apparatus for RC extraction
    Patent number: 8793640
    Abstract: The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Yu Liu, Ke-Ying Su, Austin Chingyu Chiang, Hsiao-Shu Chao
  • Method and equipment for image-guided stereotactic radiosurgery of breast cancer
    Patent number: 8788017
    Abstract: A method of treating a cancerous region in a breast of a patient comprising (i) imaging the breast in a three-dimensional coordinate system, (ii) stereotactically determining the location of the cancerous region in the breast, (iii) optionally determining the volume of the entire cancerous region to be treated, and (iv) while maintaining the breast in a three-dimensional coordinate system that is identical to or corresponds with the three-dimensional coordinate system used in (i), noninvasively exposing the cancerous region of the breast of the patient to a cancer-treatment effective dose of radiation; and equipment for use in such a method.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: July 22, 2014
    Assignees: University of Maryland, Baltimore, Xcision Medical Systems, LLC
    Inventors: Xinsheng Cedric Yu, Ying Su Yu, William Regine
  • RC corner solutions for double patterning technology
    Patent number: 8751975
    Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
  • Systems and methods for creating frequency-dependent netlist
    Patent number: 8745559
    Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Cheng Chou, Ke-Ying Su
  • Method and system for photomask assignment for double patterning technology
    Patent number: 8732628
    Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Fan Wu, I-Fan Lin, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
  • RC EXTRACTION METHODOLOGY FOR FLOATING SILICON SUBSTRATE WITH TSV
    Publication number: 20140082578
    Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ze-Ming Wu, Ching-Shun Yang, Ke-Ying Su, Hsiao-Shu Chao
  • Method of generating RC technology file
    Patent number: 8671382
    Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Yung-Chin Hou
  • RC extraction methodology for floating silicon substrate with TSV
    Patent number: 8607179
    Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ze-Ming Wu, Ching-Shun Yang, Ke-Ying Su, Hsiao-Shu Chao
  • SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST
    Publication number: 20130305196
    Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die including at least one metal layer to be formed using at least one of a single patterning process or a multi-patterning process, creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the metal layer of at least one die based on the technology file, simulating a performance of the integrated circuit based on the netlist, adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and repeating the simulating and adjusting to optimize the at least one of the capacitive or inductive couplings.
    Type: Application
    Filed: April 29, 2013
    Publication date: November 14, 2013
    Inventors: Chih-Cheng CHOU, Ke-Ying SU
  • Method and apparatus for quantitative analysis of breast density morphology based on MRI
    Patent number: 8582858
    Abstract: A method and apparatus configured to analyze breast density based on magnetic resonance imaging (MRI) of a breast of a patient includes the steps of segmenting an MR image of the breast from one set of three-dimensional breast MRI images, and analyzing the amount of dense tissue and the morphological distribution of the dense tissue and a data processor configured by software to perform these steps. Analyzing the amount of dense tissue and the morphological distribution of the dense tissue includes the steps of segmenting tissue data to separate breast tissue from other body tissue, separating tissue data of the dense and fatty tissues in the breast, and analyzing the morphological distribution of dense tissue in the breast to derive one or more three dimensional morphological parameters of the dense tissue distribution.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: November 12, 2013
    Assignee: The Regents of the University of California
    Inventors: Min-Ying Su, Ke Nie
  • Accurate parasitic capacitance extraction for ultra large scale integrated circuits
    Patent number: 8572537
    Abstract: A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Ying Su, Chia-Ming Ho, Gwan-Sin Chang, Chien-Wen Chen
  • RC Corner Solutions for Double Patterning Technology
    Publication number: 20130275927
    Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.
    Type: Application
    Filed: May 23, 2012
    Publication date: October 17, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
  • Sputtering Target Having Alarm Function
    Publication number: 20130206589
    Abstract: The present invention provides a sputtering target having alarm function. The sputtering target comprises: a target body including a target material and having a bonding plane; a backing body bonded with the bonding plane of the target body; and at least one alarm body embedded in the target body. Wherein, a length of each alarm body, ratios of an area of each alarm body and the sum of area(s) of the at least one alarm body projected onto the bonding plane relative to an area of the bonding plane are controlled in a suitable range. Thus, the bonding strength and the heat-removing efficiency of the sputtering target can be maintained, and the distinguishable material of the alarm body can evolve a gas component distinguishable from a sputtering environment serving as an alarm signal for stopping the sputtering process in time.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 15, 2013
    Applicant: Solar Applied Materials Technology Corp.
    Inventors: Shu-Hua Hu, Ming-Chang Lu, Pai-Ying Su, Jung-Sheng Chen, Hsin-Chun Yin
  • Systems and methods for creating frequency-dependent RC extraction netlist
    Patent number: 8495532
    Abstract: A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: July 23, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
  • METHOD OF GENERATING A BIAS-ADJUSTED LAYOUT DESIGN OF A CONDUCTIVE FEATURE AND METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS
    Publication number: 20130174112
    Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.
    Type: Application
    Filed: February 10, 2012
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming HO, Ke-Ying SU, Hsiao-Shu CHAO, Yi-Kan CHENG
  • RC Extraction Methodology for Floating Silicon Substrate with TSV
    Publication number: 20130139121
    Abstract: The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 30, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ze-Ming Wu, Ching-Shun Yang, Ke-Ying Su, Hsiao-Shu Chao
  • Systems and methods for creating frequency-dependent netlist
    Patent number: 8453095
    Abstract: A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ke-Ying Su, Ching-Shun Yang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng, Huang-Yu Chen, Chung-Hsing Wang