Abstract: A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.

Abstract: Provided herein are methods and compositions related to a retinoid receptor-selective pathway. As described herein, this pathway can be targeted to manipulate a tumor microenvironment. For example, the methods and compositions described herein can be used to induce apoptosis in a cancer cell. Further, the compositions described herein, including Sulindac and analogs thereof, can be used to target this pathway for the treatment or prevention of cancer in human patients.

Abstract: A method of designing a circuit layout includes calculating a typical value representing performance characteristics for the circuit layout based on a graphic database system (GDS) file. The method further includes calculating an adjustment value based on the GDS file and at least one of a CAP corner vector or a RES corner vector, wherein the CAP corner vector is based on an eigenvector of a parasitic capacitance of the circuit layout, and the RES corner vector is based on an eigenvector of a parasitic resistance of the circuit layout. The method further includes calculating a corner value based on the typical value and the adjustment value. The method further includes modifying the GDS file if performance characteristics of the corner value fail to satisfy performance requirements of the circuit layout.

Abstract: A layout of an integrated circuit design is provided and a plurality of multiple patterning decompositions is determined from the layout. Each decomposition of the plurality of multiple patterning decompositions includes patterns separated into masks. One or more files are generated that include sensitivities of pattern capacitances to changes in spacing between patterns due to mask shifts. Using the sensitivities and changes in spacing, respective worst-case performance values are determined for each decomposition. A mask set is selected based on the worst-case performance values.

Abstract: An electronic device includes a substrate, a first device, a second device, and a shielding wall. The first device and the second device are disposed on the substrate respectively. The shielding wall is disposed independently between the first device and the second device. The shielding wall is configured for suppressing the electromagnetic interference from the second device to the first device.

Abstract: Embodiments provided herein relate to methods and compositions for treating cancer. Some embodiments relate to certain compounds having activity against retinoid X receptor-alpha (RXR?). Some embodiments included designing or identifying a compound that binds to human RXRa protein, such as the ligand binding domain (LBD) of human RXRa protein.

Abstract: A semiconductor light-emitting device including a substrate, a first-type doped semiconductor structure, a light-emitting layer, and a second-type doped semiconductor layer is provided. The first-type doped semiconductor structure is located on the substrate and includes a base and multi-section rod structures extended upward from the base. Each multi-section rod structure includes rods and at least one connecting portion. The connecting portion connects adjacent rods along a first direction, wherein the first direction is perpendicular to the base and points to the connecting portion from the base. Cross-section areas of different rods on a reference plane parallel to the substrate are different, and cross-section areas of the connecting portion on the reference plane decrease along the first direction. The light-emitting layer is located on sidewalls of the rods. The second-type doped semiconductor layer is located on the light-emitting layer.

Abstract: A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.

Abstract: A system and method comprising providing a layout of an integrated circuit design, generating, by a processor, a plurality of multiple patterning decompositions from the layout, determining a maximum mask shift between the first mask and the second mask and simulating a worst-case performance value for each of the plurality of multiple patterning decompositions using one or more mask shifts within a range defined by the maximum mask shift. Further, each of the plurality of multiple patterning decompositions comprise patterns separated to a first mask and a second mask of a multiple patterning mask set.

Abstract: A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.

Abstract: A cover film with high dimensional stability includes an insulation film, a first adhesive layer, and a carrier. A first side of the first adhesive layer is connected to a first surface of the insulation film, and a second side of the first adhesive layer is configured to adhere to at least one metal conductor of a flexible printed circuit board. The carrier includes a supporting film and a second adhesive layer. A first side of the second adhesive layer is connected to the supporting film, and a second side of the second adhesive layer is adhered to a second surface of the insulation film, wherein bonding strength of the second adhesive film is smaller than bonding strength of the first adhesive film.

Abstract: A process for manufacturing a heat insulation container mainly includes preparing a coating material by mixing a binder and a thermo-expandable powder, coating such coating material on a surface of a container and then heating the container to foam the coated material after the container is shaped. The foamed coating material is therefore provides the container with heat insulation property. The thermo-expandable powder consists of a plurality of thermo-expandable microcapsules, each of which consists of a thermoplastic polymer shell and a solvent wrapped by the thermoplastic polymer shell. To obtain a smooth surface, the soften point of the binder is required to be lower than the boiling point of the solvent.

Abstract: A method of designing a circuit layout includes calculating a typical value representing performance characteristics for the circuit layout based on a graphic database system (GDS) file. The method further includes calculating an adjustment value based on the GDS file and at least one of a CAP corner vector or a RES corner vector, wherein the CAP corner vector is based on an eigenvector of a parasitic capacitance of the circuit layout, and the RES corner vector is based on an eigenvector of a parasitic resistance of the circuit layout. The method further includes calculating a corner value based on the typical value and the adjustment value. The method further includes modifying the GDS file if performance characteristics of the corner value fail to satisfy performance requirements of the circuit layout.

Abstract: A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The generating the file is performed using a computer. The file includes at least two of a first capacitance table, a second capacitance table, and a third capacitance table. The first capacitance table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks including the layout patterns shift relative to each other. The second capacitance table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The third capacitance table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other.

Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.

Abstract: A file classifying system and a file classifying method are disclosed herein, where the system includes a storing device storing at least one recognizing audio signal, a receiving device, and a processor. The receiving device receives an audio file or a video file. The processor compares a related audio signal and the at least one recognizing audio signal so as to generate a result of process, where the related audio signal is correlated to the audio file or the video file, and then automatically classifies the audio file or video file into a category.

Abstract: A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.

Abstract: A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.

Abstract: Method and apparatus for securing a disc stack to a spindle motor hub. In some embodiments, a disc clamp assembly includes a spring clamp with an annular contact portion which contactingly engages a disc stack and a central aperture through which a hub projection of the spindle motor hub extends. A plurality of interlocking semi-annular shim segments interlock together to form a continuous retention ring assembly which wedges between the spring clamp and a shoulder surface of the spindle motor hub.

Abstract: A semiconductor device including a Si (110) substrate, a buffer layer, a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer is provided. The Si (110) substrate has a plurality of trenches. Each trench at least extends along a first direction, and the first direction is parallel to a <1-10> crystal direction of the Si (110) substrate. The buffer layer is located on the Si (110) substrate and exposes the trenches. The first type doped semiconductor layer is located on the buffer layer and covers the trenches. The light-emitting layer is located on the first type doped semiconductor layer. The second type doped semiconductor layer is located on the light-emitting layer. A fabrication method of a semiconductor device is also provided.