Patents by Inventor Ying-Tsung Chen
Ying-Tsung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9349833Abstract: A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.Type: GrantFiled: February 5, 2015Date of Patent: May 24, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Hsiang Hung, Chao-Hung Lin, Ying-Tsung Chen, Chih-Kai Hsu, Ssu-I Fu, Jyh-Shyang Jenq, Shih-Hung Tsai
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Patent number: 9312365Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: GrantFiled: September 16, 2014Date of Patent: April 12, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Patent number: 9278423Abstract: A method for breaking up Chemical Mechanical Polishing (CMP) slurry particles includes receiving a CMP slurry comprising particles suspended in a solution, placing the slurry into a first agitation tank, and agitating the slurry at a first frequency. The first frequency is selected to break up particles having a size within a specified range.Type: GrantFiled: October 8, 2013Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Kuo-Min Lin, Ying-Tsung Chen
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Patent number: 9269791Abstract: A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET.Type: GrantFiled: July 10, 2012Date of Patent: February 23, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ssu-I Fu, En-Chiuan Liou, Chih-Wei Yang, Ying-Tsung Chen, Shih-Hung Tsai
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Patent number: 9209040Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler. The first cushion layer is peripherally enclosed by the semiconductor substrate, the second cushion layer is peripherally enclosed by the first cushion layer, and insulating filler is peripherally enclosed by the second cushion layer. A method for fabricating the semiconductor device is also provided herein.Type: GrantFiled: October 11, 2013Date of Patent: December 8, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Min Lin, Wei-Lun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Publication number: 20150279686Abstract: One or more methods for semiconductor processing are provided. At least one of the methods include receiving information regarding a pre-etch back thickness of a first layer over a substrate, comparing the pre-etch back thickness to a desired thickness of the first layer, responsive to the pre-etch back thickness being greater than the desired thickness, determining parameters for an etch back process and performing the etch back process on the first layer to reduce the pre-etch back thickness to a first etch back thickness. The etch back process comprising performing a gas cluster ion beam etching process. In some embodiments, a second etch back process is performed. In some embodiments a wet clean process is performed on the first layer after the etch back process.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Inventors: Cheng-Yu Kuo, Teng-Chun Tsai, Ying-Ho Chen, Kuo-Min Lin, Ying-Tsung Chen, Bing-Hung Chen
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Publication number: 20150187594Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.Type: ApplicationFiled: December 26, 2013Publication date: July 2, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9054187Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.Type: GrantFiled: November 26, 2013Date of Patent: June 9, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
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Patent number: 9024393Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.Type: GrantFiled: December 26, 2013Date of Patent: May 5, 2015Assignee: United Microelectronics Corp.Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
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Publication number: 20150102456Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler. The first cushion layer is peripherally enclosed by the semiconductor substrate, the second cushion layer is peripherally enclosed by the first cushion layer, and insulating filler is peripherally enclosed by the second cushion layer. A method for fabricating the semiconductor device is also provided herein.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Min LIN, Wei-Lun HONG, Ying-Tsung CHEN, Liang-Guang CHEN
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Patent number: 9006091Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.Type: GrantFiled: June 11, 2014Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Chien-Ting Lin, Wen-Tai Chiang
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Publication number: 20150099431Abstract: A method for breaking up Chemical Mechanical Polishing (CMP) slurry particles includes receiving a CMP slurry comprising particles suspended in a solution, placing the slurry into a first agitation tank, and agitating the slurry at a first frequency. The first frequency is selected to break up particles having a size within a specified range.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Kuo-Min Lin, Ying-Tsung Chen
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Patent number: 8987096Abstract: A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.Type: GrantFiled: February 7, 2012Date of Patent: March 24, 2015Assignee: United Microelectronics Corp.Inventors: Ying-Tsung Chen, Chien-Ting Lin, Ssu-I Fu, Shih-Hung Tsai, Wen-Tai Chiang, Chih-Wei Chen, Chiu-Hsien Yeh, Shao-Wei Wang, Kai-Ping Wang
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Patent number: 8975179Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.Type: GrantFiled: October 18, 2011Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hao Tu, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Publication number: 20150037978Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: August 5, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHE-HAO TU, WILLIAM WEILUN HONG, YING-TSUNG CHEN
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Publication number: 20150004766Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Publication number: 20140370696Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Inventors: Che-Hao TU, Chih-Yu CHANG, William Weilun HONG, Ying-Tsung CHEN
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Publication number: 20140339652Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.Type: ApplicationFiled: August 1, 2014Publication date: November 20, 2014Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
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Patent number: 8877623Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.Type: GrantFiled: May 14, 2012Date of Patent: November 4, 2014Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Chien-Ting Lin, Wen-Tai Chiang
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Patent number: 8872280Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: GrantFiled: July 31, 2012Date of Patent: October 28, 2014Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen