Patents by Inventor Ying-Tsung Chen
Ying-Tsung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140295660Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Chien-Ting Lin, Wen-Tai Chiang
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Publication number: 20140199817Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.Type: ApplicationFiled: March 19, 2014Publication date: July 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Chien-Liang Lin, Chien-Ting Lin, Ssu-I Fu, Ying-Tsung Chen
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Patent number: 8722501Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.Type: GrantFiled: October 18, 2011Date of Patent: May 13, 2014Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Chien-Liang Lin, Chien-Ting Lin, Ssu-I Fu, Ying-Tsung Chen
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Publication number: 20140106557Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.Type: ApplicationFiled: December 26, 2013Publication date: April 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
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Publication number: 20140077229Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.Type: ApplicationFiled: November 26, 2013Publication date: March 20, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
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Patent number: 8669618Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.Type: GrantFiled: December 15, 2011Date of Patent: March 11, 2014Assignee: United Microelectronics Corp.Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
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Patent number: 8664060Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.Type: GrantFiled: February 7, 2012Date of Patent: March 4, 2014Assignee: United Microelectronics Corp.Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
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Publication number: 20140035066Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Ying-Chih Lin, Chien-Ting Lin, Hsuan-Hsu Chen
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Publication number: 20140015056Abstract: A multi-gate MOSFET includes a substrate, a dielectric layer and at least a fin-shaped structure. The substrate has a first area and a second area. The dielectric layer is only located in the substrate of the first area. At least a fin-shaped structure is located on the dielectric layer. Moreover, the present invention also provides a multi-gate MOSFET process forming said multi-gate MOSFET.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Inventors: Ssu-I Fu, En-Chiuan Liou, Chih-Wei Yang, Ying-Tsung Chen, Shih-Hung Tsai
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Patent number: 8598028Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.Type: GrantFiled: December 22, 2011Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Hao Tu, Chi-Jen Liu, Tzu-Chung Wang, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Publication number: 20130302976Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.Type: ApplicationFiled: May 14, 2012Publication date: November 14, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen, Chien-Ting Lin, Wen-Tai Chiang
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Publication number: 20130203230Abstract: A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Inventors: Ying-Tsung Chen, Chien-Ting Lin, Ssu-I Fu, Shih-Hung Tsai, Wen-Tai Chiang, Chih-Wei Chen, Chiu-Hsien Yeh, Shao-Wei Wang, Kai-Ping Wang
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Publication number: 20130200470Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.Type: ApplicationFiled: February 7, 2012Publication date: August 8, 2013Inventors: An-Chi Liu, Chun-Hsien Lin, Yu-Cheng Tung, Chien-Ting Lin, Wen-Tai Chiang, Shih-Hung Tsai, Ssu-I Fu, Ying-Tsung Chen, Chih-Wei Chen
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Publication number: 20130164930Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures.Type: ApplicationFiled: December 22, 2011Publication date: June 27, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Che-Hao Tu, Chi-Jen Liu, Tzu-Chung Wang, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Patent number: 8470714Abstract: A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.Type: GrantFiled: May 22, 2012Date of Patent: June 25, 2013Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Ssu-I Fu, Chien-Liang Lin, Ying-Tsung Chen, Ted Ming-Lang Guo, Chin-Cheng Chien, Chien-Ting Lin, Wen-Tai Chiang
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Publication number: 20130154012Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Inventors: Ssu-I Fu, Wen-Tai Chiang, Ying-Tsung Chen, Shih-Hung Tsai, Chien-Ting Lin, Chi-Mao Hsu, Chin-Fu Lin
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Publication number: 20130095644Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Che-Hao Tu, Weilun Hong, Ying-Tsung Chen, Liang-Guang Chen
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Publication number: 20130095616Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Inventors: Shih-Hung Tsai, Chien-Liang Lin, Chien-Ting Lin, Ssu-I Fu, Ying-Tsung Chen
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Publication number: 20120256276Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.Type: ApplicationFiled: April 7, 2011Publication date: October 11, 2012Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
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Patent number: 8278184Abstract: A method of forming a non-planar transistor is provided. A substrate is provided. The substrate has a plurality of isolation regions to be formed and a plurality of fin regions to be formed. A first etching process is performed to form a plurality of first trenches having a first depth in the substrate within the isolation regions. At least a doping region is formed in the substrate within the fin regions. A second etching process is performed to deepen the first depth to a second depth and a plurality of fin structures are formed in the substrate within the fin regions. Lastly, a gate is formed on the fin structures.Type: GrantFiled: November 2, 2011Date of Patent: October 2, 2012Assignee: United Microelectronics Corp.Inventors: Ying-Tsung Chen, Chien-Ting Lin, Shih-Hung Tsai, Ssu-I Fu, Wen-Tai Chiang