Abstract: A battery positioning apparatus for positioning a battery. The battery includes a first grip surface and a second grip surface. Projections of the first grip surface and the second grip surface along a first direction do not overlap. The first direction is perpendicular to the first grip surface and the second grip surface. The battery positioning apparatus includes a pallet and a limiting mechanism. The pallet is configured to hold a battery. The limiting mechanism is disposed on the pallet and configured to release the first grip surface of the battery when the second grip surface of the battery is gripped along the first direction.

Abstract: The present application disclose a battery box transferring device, including: a translation mechanism configured to move a battery box in a first direction and/or a second direction, the first direction being perpendicular to the second direction; a rotating mechanism arranged on the translation mechanism, the rotating mechanism comprising: a first rotating assembly and a second rotating assembly, wherein the first rotating assembly is configured to rotate the battery box about the first direction as an axis, and the second rotating assembly is configured to rotate the battery box about the second direction as an axis; and a battery box moving mechanism arranged on the rotating mechanism, the battery box moving mechanism being configured to pull the battery box into or push the battery box out of the battery box transferring device. The battery box transferring device can effectively move the battery box on various site conditions while effectively saving manpower.

Abstract: To reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

Abstract: The present disclosure provides a high-efficiency and low-damage potato combine harvester, including a digging device, a conveyance and separation device, a separation and elevation reversing device, a potato collection box, and a control unit. The present disclosure can realize low-damage digging, high-efficiency conveyance, and high-performance potato-soil and potato-stem separation at a time, can effectively reduce a digging resistance in potato harvesting and prevent soil hilling and potato damaging phenomena, and improves conveyance and separation efficiencies for a potato-soil-stem mixture. The present disclosure makes the harvester more adaptable to different soil properties and potato varieties, allows an operator to better adjust working performance of the harvester, reduces a falling damage of potatoes due to a large falling height in box packaging, and meets requirements of high-efficiency combine harvesting of the potatoes.

Abstract: The present disclosure provides a high-efficiency and low-damage potato combine harvester, including a digging device, a conveyance and separation device, a separation and elevation reversing device, a potato collection box, and a control unit. The digging device is provided at a front end of the potato combine harvester. The conveyance and separation device is provided behind the digging device, and configured to perform preliminary conveyance and separation on a potato-soil-stem mixture dug by the digging device. The separation and elevation reversing device is provided at a side of the conveyance and separation device, and configured to separate the potato-soil-stem mixture from the conveyance and separation device and elevate potatoes to the potato collection box. The potato collection box is located at a tail end of the separation and elevation reversing device, and configured to load the potatoes and feed weight information of carried potatoes back to the control unit.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

Abstract: A method of fabricating a semiconductor device includes forming an interconnect structure over a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching trenches into the sensor substrate, pre-cleaning an exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming isolation structures within the etched trenches.

Abstract: An optical distortion correction system includes a correction device that generates correction values according to data from a lens; a weighting device that generates weights for corresponding data according to the correction values; a jag detector that detects a jag in an outline according to the data; a filter that provides a spatial filter when a jag is detected; and a smoothing device that smooths the data by the weights and the spatial filter, thereby resulting in smoothed data.

Abstract: Embodiments of the present application provide a pickup tooling, which relate to the field of pickup devices. The pickup tooling includes a base and a pickup mechanism. A mounting portion is arranged on one side of the base in a first direction, and the mounting portion is used for connecting an execution end of the robot. The pickup mechanism includes a mounting seat, a pickup unit, and a driving mechanism. The mounting seat is connected to the base, and the pickup unit is connected to the mounting seat in a flippable manner and is used for picking up a workpiece. The driving mechanism is configured to drive the pickup unit to rotate about a central axis to change the posture of the pickup unit, with the central axis perpendicular to the first direction. The pickup unit is flippable about the central axis and connected to the mounting seat.

Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.

Abstract: An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: Systems and methods for increasing peak ion energy with a low angular spread of ions are described. In one of the systems, multiple radio frequency (RF) generators that are coupled to an upper electrode associated with a plasma chamber are operated in two different states, such as two different frequency levels, for pulsing of the RF generators. The pulsing of the RF generators facilitates a transfer of ion energy during one of the states to another one of the states for increasing ion energy during the other state to further increase a rate of processing a substrate.

Abstract: A method for performing wireless communication in MLO architecture is applicable to an AP MLD connected with a non-AP MLD through multiple links. The multiple links include at least a first link and a second link, the non-AP MLD operates in ML-SMPS mode. The method includes transmitting an initial control frame to the non-AP MLD via the first link, to trigger at least one link of the multiple links to be activated at the non-AP MLD to support a reception with respective negotiated number of spatial streams, receiving a response frame via the first link in response to the transmission of the initial control frame, and initiating frame exchange between the AP MLD and the non-AP MLD via a target link of the at least one link. The target link is selected from the at least one link according to the response frame. The first link is a primary link.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.

Abstract: A multi-link operation (MLO) transmission method is provided. The MLO transmission method may be applied to an apparatus. The MLO transmission method may include the following steps. A plurality of station (STA) modules of the apparatus may each perform a respective backoff procedure. Each STA module may correspond to a different link. An MLO control circuit of the apparatus or a first STA module of the plurality of STA modules may determine whether to perform a synchronous transmission (TX) for a first STA module and at least one of other STA modules in response to a first backoff counter of the first STA module reaching 0.

Abstract: A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a <110> direction.

Abstract: Methods for selectively depositing an epitaxial layer are provided. In some implementations, the selective epitaxial deposition process includes providing the co-flow of chlorosilane precursors with at least one of an antimony-containing precursor and a phosphorous-containing precursor. The method utilizes co-flowing of multiple chlorosilane precursors to enable combination of silicon and at least one of phosphorous and antimony in the same matrix using a low-temperature selective process. The deposited epitaxial layer using the epitaxial deposition techniques described not only contains phosphorous and/or antimony but also has a high activated phosphorous and/or antimony concentration.