Abstract: An isolated and purified lactic acid bacteria is provided, which is Lactobacillus paracasei PS23 (PS23) and its applications in delaying aging process, improving immunomodulatory activity, reducing, preventing or treating allergic and inflammation, preventing or treating a chronic disorder and/or (vi) preventing and/or treating a mood disorder or a neurological condition.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

Abstract: A laser processing system includes a laser source, an optical splitting unit, a frequency conversion unit and at least one optical mixer. The optical splitting unit is provided to divide light emitted by the laser source into a first light and a second light, and the first light and the second light have the same wavelength range. The frequency conversion unit is provided to convert the second light into a working light. The working light includes a frequency converted light, and the frequency converted light and the second light have different wavelength ranges. The optical mixer is provided to mix the first light with the frequency converted light.

Abstract: The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively.

Abstract: The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively.

Abstract: A stacked chip layout includes a central processing chip, a first active circuit block over the central processing chip, and a second active circuit block overlapping the first active circuit. The first and second active circuit blocks are within a perimeter of the central processing chip in a plan view. The stacked chip layout includes a first routing region on a same plane as the first active circuit block, and a second routing region on a same plane as the second active circuit block. The first routing region is between the second active circuit block and the central processing chip. The stacked chip layout includes a heat dissipation element over the second active circuit block and the second routing region. The second routing region is configured to convey heat from the first active circuit block to the heat dissipation element.

Abstract: A stacked chip layout includes a central processing chip, a first active circuit block over the central processing chip, and a second active circuit block overlapping the first active circuit. The first and second active circuit blocks are within a perimeter of the central processing chip in a plan view. The stacked chip layout includes a first routing region on a same plane as the first active circuit block, and a second routing region on a same plane as the second active circuit block. The first routing region is between the second active circuit block and the central processing chip. The stacked chip layout includes a heat dissipation element over the second active circuit block and the second routing region. The second routing region is configured to convey heat from the first active circuit block to the heat dissipation element.

Abstract: A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

Abstract: A transceiver and a clock generation module are provided. The transceiver includes a receiver and the clock generation module. The receiver receives a receiving-input-data and a receiving-input-strobe. The receiver includes a data-receiving circuit for delaying the receiving-input-data and a strobe-receiving circuit for delaying the receiving-input-strobe. The clock generation module includes a calibration circuit, a phase-compensation module, and a multi-phase signal generator. The phase-compensation module compensates one of the data-receiving circuit and the strobe-receiving circuit according to a data-phase-compensation signal and a strobe-phase-compensation signal generated by the calibration circuit. The multi-phase signal generator generates shifted system-clock signals. A phase difference between the first and the second shifted system-clock signals is equivalent to a phase difference between the receiving-path-data and the receiving-path-strobe.

Abstract: A transceiver and a clock generation module are provided. The transceiver includes a receiver and the clock generation module. The receiver receives a receiving-input-data and a receiving-input-strobe. The receiver includes a data-receiving circuit for delaying the receiving-input-data and a strobe-receiving circuit for delaying the receiving-input-strobe. The clock generation module includes a calibration circuit, a phase-compensation module, and a multi-phase signal generator. The phase-compensation module compensates one of the data-receiving circuit and the strobe-receiving circuit according to a data-phase-compensation signal and a strobe-phase-compensation signal generated by the calibration circuit. The multi-phase signal generator generates shifted system-clock signals. A phase difference between the first and the second shifted system-clock signals is equivalent to a phase difference between the receiving-path-data and the receiving-path-strobe.

Abstract: A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

Abstract: A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

Abstract: A delay signal generating apparatus has a digitally controlled delay line and a control circuit. The digitally controlled delay line has a coarse delay circuit and a fine delay circuit. The coarse delay circuit generates a plurality of coarse delay signals by applying a plurality of different coarse delay amounts to an input signal, respectively, wherein the different coarse delay amounts are set by a first control input. The fine delay circuit generates a fine delay signal having a fine delay amount with respect to the input signal by performing phase interpolation based on the coarse delay signals, wherein the fine delay amount is set by a second control input. The control circuit generates the first control input to the coarse delay circuit, and generates the second control input to the fine delay circuit, wherein the control circuit does not change the first control input unless one of the coarse delay signals has no contribution to the fine delay signal according to the second control input.

Abstract: A delay signal generating apparatus has a digitally controlled delay line and a control circuit. The digitally controlled delay line has a coarse delay circuit and a fine delay circuit. The coarse delay circuit generates a plurality of coarse delay signals by applying a plurality of different coarse delay amounts to an input signal, respectively, wherein the different coarse delay amounts are set by a first control input. The fine delay circuit generates a fine delay signal having a fine delay amount with respect to the input signal by performing phase interpolation based on the coarse delay signals, wherein the fine delay amount is set by a second control input. The control circuit generates the first control input to the coarse delay circuit, and generates the second control input to the fine delay circuit, wherein the control circuit does not change the first control input unless one of the coarse delay signals has no contribution to the fine delay signal according to the second control input.

Abstract: The present disclosure relates to a system which includes a memory controller interface, a memory unit interface, and a correction block. The memory controller interface includes a digitally-controlled delay line (DCDL). The memory unit interface is coupled to the memory controller interface, and is configured to communicate with the memory controller interface through a first signal and a second signal. The correction block is configured to determine a result of alignment between the first signal and the second signal, and to provide a correction signal configured to align the first signal to the second signal. Other systems, devices and methods are disclosed.

Abstract: A system for capturing an eye diagram is disclosed.

Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.

Abstract: The present disclosure relates to a system which includes a memory controller interface, a memory unit interface, and a correction block. The memory controller interface includes a digitally-controlled delay line (DCDL). The memory unit interface is coupled to the memory controller interface, and is configured to communicate with the memory controller interface through a first signal and a second signal. The correction block is configured to determine a result of alignment between the first signal and the second signal, and to provide a correction signal configured to align the first signal to the second signal. Other systems, devices and methods are disclosed.

Abstract: The present disclosure relates to an interface comprising a memory controller and a memory unit coupled to the memory controller and configured to communicate with the memory controller through a first signal and a second signal. The interface further comprises a determination unit comprising judgment logic configured to send a control signal configured to align the first signal with the second signal. The memory controller further comprises a digitally-controlled delay line (DCDL) coupled to the determination unit and configured to receive the control signal, wherein the determination unit instructs the DCDL to adjust a delay of the first signal to align the first signal with the second signal. The memory controller further comprises a value register configured to store a signal delay value corresponding to alignment between the first signal with the second signal which is contained within the control signal. Other devices and methods are disclosed.