Abstract: An integrated circuit includes a first connection line; a second connection line; a plurality of tuning resistors with each having a sequence number and being coupled between the first connection line and the second connection line; and a plurality of switches, with each being coupled in series with one of the plurality of tuning resistors. The sequence numbers of the plurality of tuning resistors are continuous. The resistance values of the plurality of tuning resistors are a function of the respective sequence numbers.

Abstract: A circuit includes a reference voltage generator configured to generate a first reference voltage and a second reference voltage, wherein the first reference voltage is higher than a half of a positive power supply voltage, and the second reference voltage is lower than the half of the positive power supply voltage. An n-type differential amplifier includes a first and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to an input node, and a gate of the second NMOS transistor is configured to receive the first reference voltage. A p-type differential amplifier is operated by the positive supply voltage and includes a first and a second PMOS transistor. A gate of the first PMOS transistor is coupled to the input node, and a gate of the second PMOS transistor is configured to receive the second reference voltage.

Abstract: A circuit includes a reference voltage generator configured to generate a first reference voltage and a second reference voltage, wherein the first reference voltage is higher than a half of a positive power supply voltage, and the second reference voltage is lower than the half of the positive power supply voltage. An n-type differential amplifier includes a first and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to an input node, and a gate of the second NMOS transistor is configured to receive the first reference voltage. A p-type differential amplifier is operated by the positive supply voltage and includes a first and a second PMOS transistor. A gate of the first PMOS transistor is coupled to the input node, and a gate of the second PMOS transistor is configured to receive the second reference voltage.

Abstract: An integrated circuit includes a first connection line; a second connection line; a plurality of tuning resistors with each having a sequence number and being coupled between the first connection line and the second connection line; and a plurality of switches, with each being coupled in series with one of the plurality of tuning resistors. The sequence numbers of the plurality of tuning resistors are continuous. The resistance values of the plurality of tuning resistors are a function of the respective sequence numbers.

Abstract: An integrated circuit includes a pad coupled with a driver. The driver is capable of driving data to the pad. The driver is capable of providing a first set of resistance data substantially fitting to a first curve and a second set of resistance data substantially fitting to a second curve. A portion of at least one of the first set of resistance data and the second set of resistance data is an impedance of the driver to drive data.

Abstract: An integrated circuit includes a pad coupled with a driver. The driver is capable of driving data to the pad. The driver is capable of providing a first set of resistance data substantially fitting to a first curve and a second set of resistance data substantially fitting to a second curve.