Patents by Inventor Ying Yu

Ying Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11307983
    Abstract: A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ning Chen, Jiangli Zhu, Ying Yu Tai
  • Publication number: 20220112655
    Abstract: A method and an integrated system for dyeing synthetic, natural, and blended textiles in the form of fabrics, yarns, and garments are provided. The integrated system includes a first pressurizing pump for pressurizing liquefied CO2 to supercritical CO2 (Sc—CO2); a second pressurizing pump for pressurizing CO2 to liquefied CO2; a liquefied CO2 storage vessel for storing the liquefied CO2 and the separated liquefied CO2 from the one or more cyclone separators; a heater for heating the Sc—CO2; a dyestuff vessel for mixing a dyestuff and the Sc—CO2 to obtain Sc—CO2-mixed dyestuff; a dyeing vessel for dyeing the textile by circulating the Sc—CO2 and the Sc—CO2-mixed dyestuff between the dyeing vessel and the dyestuff vessel; and one or more cyclone separators for removing the dyestuff from the Sc—CO2-mixed dyestuff to obtain separated liquefied CO2.
    Type: Application
    Filed: March 13, 2019
    Publication date: April 14, 2022
    Inventors: Edwin Yee Man KEH, Lei YAO, Alex Hok Chung CHAN, John Kin Ming LEUNG, Jason Lap Hung CHAN, Wendy Lee Ying YU
  • Patent number: 11294750
    Abstract: In an embodiment, a system includes a plurality of memory components and a processing device. The processing device includes a command-lifecycle logger component that is configured to perform command-lifecycle-logging operations, which include detecting a triggering event for logging command-lifecycle debugging data, and responsively logging command-lifecycle debugging data. Logging command-lifecycle debugging data includes generating the command-lifecycle debugging data and storing the generated command-lifecycle debugging data in data storage.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Ying Yu Tai, Jiangli Zhu, Wei Wang
  • Patent number: 11288013
    Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Jiangli Zhu, Ying Yu Tai, Wei Wang
  • Patent number: 11281533
    Abstract: Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu, Zhengang Chen
  • Publication number: 20220086149
    Abstract: Techniques for storage management involve: receiving, at a storage server, an access request for target data from a client, wherein the access request occurs in a session between the storage server and the client; determining, based on attribute information of the client, security information of the session, wherein the security information indicates whether the session is subjected to antivirus protection; and executing, based on the security information, an access operation specified by the access request on the target data. Therefore, the performance of the storage server can be improved while the security of the storage server is ensured.
    Type: Application
    Filed: January 27, 2021
    Publication date: March 17, 2022
    Inventors: Ying Yu, Jing Li, Ming Yue, Jia Huang, Nan Wang
  • Publication number: 20220075682
    Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Inventors: Jiangli Zhu, Ying Yu Tai, Fangfang Zhu, Wei Wang
  • Publication number: 20220069012
    Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
    Type: Application
    Filed: April 27, 2021
    Publication date: March 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu BAO, Hengyuan Lee, Ying-Yu Chen
  • Patent number: 11255047
    Abstract: Disclosed in one aspect is a pickled vegetable-based edible packaging paper, the raw material of which is composed of the following components in parts by weight: 92-95 parts of a high dietary fiber-level pickled vegetable, a compounding thickener (0.6-0.8 parts of pectin, 0.6-0.8 parts of potato starch, and 0.2-0.4 parts of soy protein), and a compounding plasticizer (3-4 parts of sorbitol, and 0.5-1.5 parts of citral); and further disclosed in another aspect is a method for preparing a pickled vegetable-based edible packaging paper. The pickled vegetable paper of the present invention is a novel pickled vegetable-based product having both edible and practical functions, which product is rich in dietary fibers, retains the unique flavor and color of the pickled vegetable, has toughness and non-stickiness to teeth, and is soft and easy to process after being wetted.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 22, 2022
    Assignee: SHANGHAI JIAO TONG UNIVERSITY
    Inventors: Jinhong Wu, Quan Jin, Zhengwu Wang, Qiaoyu Wu, Wei Zhang, Danlu Yang, Ying Yu, Wenhui Li, Xinzhe Gu, Shaoyun Wang, Huiyun Chen
  • Publication number: 20220051737
    Abstract: One or more write operations are performed on a memory component. First data stored at the memory component is read. A determination is made as to whether an error rate associated with the first data stored at the memory component exceeds an error rate threshold. If the error rate exceeds the error rate threshold, a threshold value is adjusted. A determination is made as to whether a number of the plurality of write operations performed on the memory component since performance of a refresh operation on the memory component exceeds the threshold value. In response to determining that the number of write operations performed on the memory component exceeds the threshold value, a memory cell of the memory component is identified based on the plurality of write operations. Second data stored at memory cells of the memory component that are proximate to the identified memory cell is refreshed.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 17, 2022
    Inventors: Fangfang Zhu, Jiangli Zhu, Ying Yu Tai
  • Patent number: 11243831
    Abstract: In an embodiment, a system includes a plurality of memory components and a processing device that is operatively coupled with the plurality of memory components. The processing device includes a host interface, an access management component, a media management component (MMC), and an MMC-restart manager that is configured to perform operations including detecting a triggering event for restarting the MMC, and responsively performing MMC-restart operations that include suspending operation of the access management component; determining whether the MMC is operating, and if so then suspending operation of the MMC; resetting the MMC; resuming operation of the MMC; and resuming operation of the access management component.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jiangli Zhu, Ying Yu Tai, Fangfang Zhu, Wei Wang
  • Publication number: 20220035572
    Abstract: A processing device, operatively coupled with a memory device, performs operations including receiving a write request from a host system at a first time, the write request identifying first data to be stored in a segment of the memory device, determining whether a pre-read voltage level of the write request satisfies a pre-read voltage level criterion pertaining to a write-to-write time interval for the segment, wherein the write-to-write time interval is defined by the first time and a second time corresponding to a last time at which the segment was written, and responsive to determining that the pre-read voltage level satisfies the pre-read voltage level criterion pertaining to the write-to-write time interval, performing a pre-read operation on the segment using the pre-read voltage level to determine second data currently stored in the segment.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 3, 2022
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Publication number: 20220035061
    Abstract: The invention provides a three-dimensional resistivity probe for in-situ monitoring comprises: a probe rod body inside which one or more subordinate controllers are provided; a control cabin inside which a main controller is provided disposed at the top of the probe rod body; and a cone tip provided at the bottom of the probe rod body; wherein the probe rod body comprising: a plurality of resistivity sensor modules, wherein each resistivity sensor module including a plurality of insulating rings, each insulating ring having a protruded part at a top end and a groove fitting into at a bottom end, three or more point-electrode grooves are formed at the top end of each insulating ring and two through holes allowing two positioning rods to insert into for assembly are opened thereon and the outer end of each point-electrode groove extends to an outer circumference of each insulating ring.
    Type: Application
    Filed: October 19, 2021
    Publication date: February 3, 2022
    Inventors: Tengfei Fu, Lei Guo, Xingyong Xu, Yanguang Dou, Wenquan Liu, Ying Yu
  • Publication number: 20220019383
    Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
    Type: Application
    Filed: October 1, 2021
    Publication date: January 20, 2022
    Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
  • Patent number: 11216218
    Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Ying Yu Tai, Ning Chen, Jiangli Zhu, Alex Tang
  • Publication number: 20210395918
    Abstract: The present disclosure provides high-purity semi-insulating single-crystal silicon carbide wafer and crystal which include one polytype single crystal. The semi-insulating single-crystal silicon carbide wafer has silicon vacancy inside, wherein the silicon-vacancy concentration is greater than 5E11 cm{circumflex over (?)}-3.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 23, 2021
    Applicant: TAISIC MATERIALS CORP.
    Inventors: Dai-Liang MA, Bang-Ying YU, Bo-Cheng LIN
  • Publication number: 20210395917
    Abstract: The present disclosure provides semi-insulating single-crystal silicon carbide bulk material and powder which include one polytype single crystal. The semi-insulating single-crystal silicon carbide bulk material has silicon vacancy inside, wherein the silicon-vacancy concentration is greater than 5E11 cm{circumflex over (?)}?3.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 23, 2021
    Applicant: TAISIC MATERIALS CORP.
    Inventors: Dai-Liang MA, Bang-Ying YU, Bo-Cheng LIN
  • Publication number: 20210395919
    Abstract: The present disclosure provides a manufacturing method of semi-insulating single-crystal silicon carbide powder comprising: providing a semi-insulating single-crystal silicon carbide bulk, wherein the semi-insulating single-crystal silicon carbide bulk has a first silicon-vacancy concentration, and the first silicon-vacancy concentration is greater than 5E11 cm{circumflex over (?)}?3; refining the semi-insulating single-crystal silicon carbide bulk to obtain a semi-insulating single-crystal silicon carbide coarse particle, wherein the semi-insulating single-crystal silicon carbide coarse particle has a second silicon-vacancy concentration and a first particle diameter, the second silicon-vacancy concentration is greater than 5E11 cm{circumflex over (?)}?3, and the first particle diameter is between 50 ?m and 350 ?m; self-impacting the semi-insulating single-crystal silicon carbide coarse particle to obtain a semi-insulating single-crystal silicon carbide powder, wherein the semi-insulating single-crystal sili
    Type: Application
    Filed: June 3, 2021
    Publication date: December 23, 2021
    Applicant: TAISIC MATERIALS CORP.
    Inventors: Dai-Liang MA, Bang-Ying YU, Bo-Cheng LIN
  • Patent number: 11199999
    Abstract: A processing device, operatively coupled with a memory device, is configured to receive a write request identifying data to be stored in a segment of the memory device. The processing device determines a write-to-write (W2W) time interval for the segment and determines whether the W2W time interval falls within a first W2W time interval range, the first W2W time interval range corresponds to a first pre-read voltage level. Responsive to the W2W time interval for the segment falling within the first W2W interval range, the processing device performs a pre-read operation on the segment using the first pre-read voltage level. The processing device identifies a subset of the data to be stored in the segment comprising bits of data that are different than corresponding bits of the data stored in the segment. The processing device further performs a write operation to store the subset of the data in the segment.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ying Yu Tai, Jiangli Zhu
  • Patent number: 11188701
    Abstract: A stacked chip layout includes a central processing chip, a first active circuit block over the central processing chip, and a second active circuit block overlapping the first active circuit. The first and second active circuit blocks are within a perimeter of the central processing chip in a plan view. The stacked chip layout includes a first routing region on a same plane as the first active circuit block, and a second routing region on a same plane as the second active circuit block. The first routing region is between the second active circuit block and the central processing chip. The stacked chip layout includes a heat dissipation element over the second active circuit block and the second routing region. The second routing region is configured to convey heat from the first active circuit block to the heat dissipation element.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ying-Yu Hsu