Patents by Inventor Ying Yu

Ying Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230400993
    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on temperature-related memory component capabilities. The controller can obtain a write temperature associated with an individual group of memory components. Based on the write temperature and a temperature threshold associated with the individual group of memory components, the controller can select an individual media management operation to perform.
    Type: Application
    Filed: August 3, 2023
    Publication date: December 14, 2023
    Inventors: Zhenming Zhou, Ying Yu Tai
  • Patent number: 11837603
    Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Yu Lai, Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
  • Publication number: 20230378182
    Abstract: A method includes forming a source/drain region for a transistor, forming a first inter-layer dielectric over the source/drain region, and forming a lower source/drain contact plug over and electrically coupling to the source/drain region. The lower source/drain contact plug extends into the first inter-layer dielectric. The method further includes depositing an etch stop layer over the first inter-layer dielectric and the lower source/drain contact plug, depositing a second inter-layer dielectric over the etch stop layer, and performing an etching process to etch the second inter-layer dielectric, the etch stop layer, and an upper portion of the first inter-layer dielectric to form an opening, with a top surface and a sidewall of the lower source/drain contact plug being exposed to the opening, and forming an upper source/drain contact plug in the opening.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Ying-Yu Lai, Chih-Hsuan Lin, Hsi Chung Chen, Chih-Teng Liao
  • Publication number: 20230364545
    Abstract: A gas purification system includes a dust removal filler, a fouling collection pan and a gas purification device. The dust removal filler has a plurality of rows of channels, each channel extending obliquely with respect to a vertical direction to form a windward surface, and a leeward surface, and a waveform plate. The peak portion of the waveform plate is attached to the leeward surface of the obliquely prismatic channel. During operation, dust adheres to a concave portion of a lower surface of the waveform plate and accumulates to form dust aggregates. When the gravity of the dust aggregates is greater than the adhesion force, the dust aggregates fall onto the windward surface of the channels and slide off from the windward surface of the channels.
    Type: Application
    Filed: September 16, 2021
    Publication date: November 16, 2023
    Inventors: Deqiang PENG, Minghua GUAN, Ping JIN, Xiangcheng LIANG, Xiuna YANG, Ying YU, Zonglin RUAN
  • Publication number: 20230371280
    Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufactruring Company, Ltd.
    Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu Bao, Hengyuan Lee, Ying-Yu Chen
  • Publication number: 20230359398
    Abstract: A determination is made of whether a memory sub-system operates in a full capacity mode or a reduced capacity mode. The full capacity mode corresponds to accessing data residing at a set of memory devices via a number of physical data channels that corresponds to a number of logical data channels. The reduced capacity mode corresponds to accessing the data via a number of physical data channels that is less than the number of logical data channels. A data structure is updated to include one or more mappings between physical data channels and logical data channels according to the determination. A memory access operation to access a data item at memory cells of at least one of the set of memory devices is executed based on the one or more mappings of the data structure.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 9, 2023
    Inventors: Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu, Ying Yu Tai
  • Publication number: 20230359356
    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on memory component reliabilities. The controller can access configuration data to determine a reliability grade associated with individual groups of the memory components. The controller can then adaptively select between different media management operations based on the reliability grade associated with each individual group of the memory components.
    Type: Application
    Filed: May 9, 2022
    Publication date: November 9, 2023
    Inventors: Zhenming Zhou, Ying Yu Tai
  • Patent number: 11808133
    Abstract: Systems and methods for performing slide drilling and for determining operational parameters to be utilized during slide drilling. An example method includes commencing operation of a processing device, whereby the processing device determines a reference rotational distance of a top drive to be utilized during slide drilling. The processing device outputs a control command to the top drive to cause the top drive to rotate a drill string. The processing device also determines the reference rotational distance based on rotational distance measurements indicative of rotational distance achieved by the top drive and torque measurements indicative of torque applied to the drill string by the top drive.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 7, 2023
    Assignee: Schlumberger Technology Corporation
    Inventors: Nathaniel Wicks, Ying Yu Fang, Jian Wu, Ginger Hildebrand, Steven Duplantis, Kam Lui
  • Patent number: 11805661
    Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Xinyu Bao, Hengyuan Lee, Ying-Yu Chen
  • Patent number: 11802370
    Abstract: A method for decolorizing a dyed textile comprising a synthetic fiber and a disperse dye, the method includes contacting the dyed textile with a super critical fluid thereby extracting at least a portion of the disperse dye from the textile into the super critical fluid and forming an at least partially decolorized textile.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: October 31, 2023
    Assignee: The Hong Kong Research Institute of Textiles and Apparel Limited
    Inventors: Edwin Yee Man Keh, Lei Yao, Hok Chung Chan, Sai Lung Fung, Un Teng Lam, Lap Hung Chan, Lee Ying Yu
  • Publication number: 20230337980
    Abstract: Disclosed is a portable rapid detection device for cognition, sleep and psychological status. The portable rapid detection device comprises a detection dial plate, an adjusting knob, woven watchbands, screw rods, sweat-absorbent linings and a sweat-absorbent quick-drying pad. The detection dial plate is of a cylindrical structure. The embedded adjusting knob is installed in the middle of the front end of the detection dial plate. The woven watchbands are installed at two ends of the detection dial plate and fixed through the screw rods. The embedded sweat-absorbent lining is installed on the inner side of the woven watchband. The sweat-absorbent quick-drying pad is installed in the middle of the bottom of the detection dial plate and fixed through magnetic attraction.
    Type: Application
    Filed: April 17, 2023
    Publication date: October 26, 2023
    Inventors: Wen WANG, Guangbin CUI, Linfeng YAN, Ying YU, Bo HU, Zhuhong CHEN, Jingting SUN, Zeshun WU
  • Publication number: 20230340681
    Abstract: A method for clean recovery of palladium is provided, including the following steps: mixing a palladium-containing material, a Ce4+-containing acidic solution, and an additive, subjecting a resulting mixture to leaching to obtain a Pd2+-containing solution, and subjecting the Pd2+-containing solution to electrolysis to obtain palladium. In the method, the palladium-containing material is subjected to solution leaching with Ce4+ as an oxidative leaching agent and a chlorine-containing additive. After leaching is complete, a Ce4+ and Pd2+-containing leaching liquor is subjected to electrolysis to realize the green regeneration of Ce4+ and palladium. The method of the present disclosure does not lead to the generation of NOx and waste liquid. The present disclosure can significantly reduce the environmental impact and production cost and has excellent economic benefits and application prospects.
    Type: Application
    Filed: March 19, 2023
    Publication date: October 26, 2023
    Applicant: INSTITUTE OF PROCESS ENGINEERING, CHINESE ACADEMY OF SCIENCES
    Inventors: Hui ZHANG, Ying YU, Tianyan XUE, Zhanpeng YAN, Tao QI
  • Publication number: 20230343637
    Abstract: Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: Ying-Yu LAI, Chih-Yun WANG, Chih-Hsuan LIN, Hsi Chung CHEN
  • Patent number: 11800666
    Abstract: An electronic module assembly is provided. The electronic module assembly may include one or more processors mounted to a laminate, a top frame mounted to the laminate and surrounding the one or more processors, and a removable lid covering the one or more processors. The removable lid includes latches arranged along a perimeter of the removable lid, the latches engage with a lip of the top frame and secure the removable lid to the module assembly, and the removable lid can only be removed from the module assembly by releasing all of the latches.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: October 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Noah Singer, Jeffrey Allen Zitz, Mark D. Schultz, John Torok, Yuet-Ying Yu, William L. Brodsky, Shawn Canfield
  • Patent number: 11782606
    Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Wei Wang, Jiangli Zhu, Ying Yu Tai
  • Patent number: 11776880
    Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
  • Patent number: 11769165
    Abstract: In an example embodiment, a specialized machine learned model, called a look-alike model, is trained using a machine learning algorithm to predict future job engagement for a user. This look-alike model is then used to create new segments on top of the segments provided by a rules-based approach. Specifically, the look-alike model is designed to take users who have been segmented by a rule-based approach into an “inactive job seeker” categorization (such as those assigned to the resting users and dormant users segments) and calculate a predicted job engagement score for these users. Based on the predicted job engagement score, a user may then be reassigned from one of the inactive job seeker categorizations to one of one or more new job seeker categorizations (such as predicted open job seekers or predicted opportunistic job seekers).
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: September 26, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chunzhe Zhang, Satej Milind Wagle, Linda Fayad, Ada Cheuk Ying Yu
  • Patent number: 11768615
    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on temperature-related memory component capabilities. The controller can obtain a write temperature associated with an individual group of memory components. Based on the write temperature and a temperature threshold associated with the individual group of memory components, the controller can select an individual media management operation to perform.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Zhenming Zhou, Ying Yu Tai
  • Patent number: 11762573
    Abstract: A method of preserving the contiguity of large pages of a workload during migration of the workload from a source host to a destination host includes the steps of: detecting at the destination host, receipt of a small page of zeros from the source host, wherein, at the source host, the small page is part of one of the large pages of the workload; and upon detecting the receipt of the small page of zeros, storing, at the destination host, all zeros in a small page that is part of one of the large pages of the workload.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: September 19, 2023
    Assignee: VMware, Inc.
    Inventors: Arunachalam Ramanathan, Yury Baskakov, Anurekh Saxena, Ying Yu, Rajesh Venkatasubramanian, Michael Robert Stunes
  • Publication number: 20230291179
    Abstract: The present invention discloses DFB laser manufacturing method based on dielectric laterally coupled grating with deterministic grating coupling coefficient, comprising: S1: performing photolithography on an epitaxial substrate of the laser without an etch-stop layer to obtain a photoresist pattern with a waveguide morphology in a predetermined geometric configuration, and then performing dry etching and removing the photoresist to obtain a substrate of a waveguide structure in the predetermined geometric configuration; S2: depositing a layer of an insulating film with a low refractive index on the substrate; S3: depositing a dielectric film with a high refractive index on the insulating film; S4: performing photolithography on the dielectric film to prepare a photoresist pattern as a laterally coupled grating morphology; S5: performing etching and removing the photoresist for the dielectric film on the photoresist pattern to prepare a dielectric laterally coupled grating for the laser, and to further prepare
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: SUN YAT-SEN UNIVERSITY
    Inventors: Ying YU, Zhuohui YANG, Lin LIU, Siyuan YU