Abstract: The specification describes a thin film Integrated Passive Device (IPD) design that achieves isolation between conductive runners by shielding the top and bottom regions of a noisy runner with metal shielding plates. The shielding plates are derived from metal interconnect layers. The invention can be implemented by merely modifying the mask pattern for the metal interconnect layers. No added elements or steps are needed to fabricate the IPDs. The invention is suitable for use in Multi-Chip Modules (MCMs) or other arrangements where digital circuits and RF circuits are in close proximity.

Abstract: The specification describes an integrated passive device (IPD) designed to allow implementation of cellular RF and Wi-Fi RF in a single hand held device. To address the problem of RF interference a thin film RF high rejection bandpass filter is formed in an IPD implementation. The IPD implementation preferably uses silicon as the substrate material. This allows the thin film RF high rejection bandpass filter to be made using silicon processing technology, and thus produce low cost filters that still meet stringent performance requirements demanded due to the co-existing RF units. In preferred embodiments of the invention, wafer level processing using silicon substrates adds to the cost effective manufacture of the highly functional IPDs.

Abstract: The specification describes a silicon-on-silicon interconnection arrangement to implement high performance RF impedance matching using off-chip passive components. The RF sections of the system are dis-integrated into separate RF functional chips, and the functional chips are flip-chip mounted on a high resistivity silicon intermediate interconnect substrate (SIIS). The passive devices for the impedance matching networks are built into the high resistivity SIIS using thin-film technology.

Abstract: A flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

Abstract: A printed circuit board has, on one surface thereof, a plurality of metallic pads forming or leading to wire traces. The printed circuit board surface is solder mask free and a substantially runless soldering alloy is used to connect I/O solder bumps on a flip chip to the metallic pads.

Abstract: The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

Abstract: The specification describes a multi-chip module (MCM) that contains an integrated passive device (IPD) as the carrier substrate (IPD MCM). Parasitic electrical interactions are controlled at one or both interfaces of the IPD either by eliminating metal from the interfaces, or by selective use of metal in parts of the MCM that are remote from the sensitive device components. The sensitive device components are primarily analog circuit components, especially RF inductor elements. In the IPD layout, the sensitive components are segregated from other components. This allows implementation of the selective metal approach. It also allows parasitic interactions on top of the IPD substrate to be reduced by selective placement of IC semiconductor chips and IC chip ground planes. In preferred embodiments of the IPD MCM of the invention, the IPD substrate is polysilicon, to further minimize RF interactions. The various methods of assembling the module may be adapted to keep the overall thickness within 1.0 mm.

Abstract: The specification describes SDIO devices and SDIO cards wherein the SDIO devices are provided with enhanced functionality, and the SDIO cards are provided with enhanced IC capacity. A variety of multi-chip-module (MCM) approaches are used to increase the IC capacity of the SDIO card.

Abstract: The specification describes a flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

Abstract: The specification describes a flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

Abstract: The specification describes an MCM package which contains both a digital MCM and an RF MCM in a stacked configuration. The package contains means for isolating RF signals from digital signals. In one case the digital MCM substrate is attached to the system substrate and the RF MCM substrate is attached to the digital MCM substrate. Solder bumps are used for attachment in an arrangement resembling a BGA. For high density packages, at least the digital MCM comprises stacked IC chips. In the embodiment with the RF MCM substrate on the top of the stack, Passive Through Interconnections (PTIs) are made through the digital MCM substrate, and electrically isolated therefrom. The passive through interconnections are made through the solder bumps between boards and interconnected using a passive (with respect to the digital MCM board) through hole. Both the RF ground and the RF input can be isolated using PTIs. For additional isolation, the solder bumps comprising the PTIs are shielded with a Faraday cage.

Abstract: The specification describes a silicon-on-silicon interconnection arrangement to implement high performance RF impedance matching using off-chip passive components. The RF sections of the system are disintegrated into separate RF functional chips, and the functional chips are flip-chip mounted on a high resistivity silicon intermediate interconnect substrate (SIIS). The passive devices for the impedance matching networks are built into the high resistivity SIIS using thin-film technology.

Abstract: The specification describes electrical testing strategies for multi-chip modules (MCMs). The MCMs are fabricated on double sided substrates, which are then solder bump bonded to a motherboard to form a BGA package. Untested chips are attached permanently to one side of the substrate to form a partially completed MCM package (PCMP), and the PCMPs are tested. PCMPs that pass are then completed by assembling known good die on the other side of the substrate.

Abstract: The specification describes a multi-chip IC package in which IC chips are flip-chip bonded to both sides of a flexible substrate. The upper (or lower) surface of the flexible substrate is bonded to a rigid support substrate with openings in the support substrate to accommodate the IC chips bonded to the upper (or lower) surface of the flexible substrate. In a preferred embodiment a plurality of IC memory chips are mounted on one side of the flexible substrate and one or more logic chips to the other. A very thin flexible substrate is used to optimize the length of through hole interconnections between the memory and logic devices. If logic chips are flip-chip mounted in the cavity formed by the openings, a heat sink plate can be used to both cap the cavity and make effective thermal contact the backside of the logic chips.

Abstract: The specification describes a flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on IC chips with Al bonding sites. The UBM of the invention comprises a copper layer applied directly to the aluminum bonding sites. Reliable bonds are obtained if the Al surface is a nascent surface. Such a surface can be provided by back sputtering an aluminum bonding site, or by a freshly sputtered aluminum layer. The copper layer is deposited on the nascent aluminum surface in e.g. a cluster tool without breaking vacuum. The UBM can be patterned using subtractive techniques.

Abstract: The specification describes an IC test apparatus having a test bed with sockets adapted to engage arrays of I/O solder balls/bumps on the IC chip. In one embodiment the sockets are provided with through holes to interconnect the solder bumps to the next board level with minimum electrical path length thereby reducing parasitic capacitive coupling. In another embodiment the sockets in the test bed are formed by intersecting V-grooves. If pairs of intersecting V-grooves are used, pyramid shaped features are produced at the bottom of each socket. Both the sharp edges formed by the intersecting V-grooves and the pyramid provide contact enhancement between the solder bumps and the test bed. The test bed can be made as a universal blank for a given solder bump pitch. The desired test circuit is formed at the next board level.

Abstract: The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.

Abstract: The specification describes packaging assemblies for micro-electronic machined mechanical systems (MEMS). The MEMS devices in these package assemblies are based on silicon MEMS devices on a silicon support and the MEMS devices and the silicon support are mechanically isolated from foreign materials. Foreign materials pose the potential for differential thermal expansion that deleteriously affects optical alignment in the MEMS devices. In a preferred embodiment the MEMS devices are enclosed in an all-silicon chamber. Mechanical isolation is also aided by using a pin contact array for interconnecting the silicon support substrate for the MEMS devices to the next interconnect level. The use of the pin contact array also allows the MEMS devices to be easily demountable for replacement or repair.

Abstract: The specification describes electrical testing strategies for multi-chip modules (MCMs). The MCMs are fabricated on double sided substrates, which are then solder bump bonded to a motherboard to form a BGA package. Untested chips are attached permanently to one side of the substrate to form a partially completed MCM package (PCMP), and the PCMPs are tested. PCMPs that pass are then completed by assembling known good die on the other side of the substrate.