Patents by Inventor Yinon Degani

Yinon Degani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020079568
    Abstract: The specification describes an MCM package which contains both a digital MCM and an RF MCM in a stacked configuration. The package contains means for isolating RF signals from digital signals. In one case the digital MCM substrate is attached to the system substrate and the RF MCM substrate is attached to the digital MCM substrate. Solder bumps are used for attachment in an arrangement resembling a BGA. For high density packages, at least the digital MCM comprises stacked IC chips. In the embodiment with the RF MCM substrate on the top of the stack, Passive Through Interconnections (PTIs) are made through the digital MCM substrate, and electrically isolated therefrom. The passive through interconnections are made through the solder bumps between boards and interconnected using a passive (with respect to the digital MCM board) through hole. Both the RF ground and the RF input can be isolated using PTIs. For additional isolation, the solder bumps comprising the PTIs are shielded with a Faraday cage.
    Type: Application
    Filed: September 26, 2001
    Publication date: June 27, 2002
    Inventors: Yinon Degani, Thomas Dixon Dudderar, Liguo Sun, Meng Zhao
  • Publication number: 20020075031
    Abstract: The specification describes a technique for burn-in electrical testing of IC dies prior to wire bonding the dies to the next interconnection level. The dies are provided with a test solder bump array interconnected to the IC contact pads of the dies. The Known Good Dies (KGD) can then be wire bonded, or alternatively flip-chip solder bump bonded, to the next interconnect level.
    Type: Application
    Filed: November 23, 2001
    Publication date: June 20, 2002
    Inventor: Yinon Degani
  • Patent number: 6396711
    Abstract: The specification describes interconnection strategies for micro-electronic machined mechanical systems (MEMS). Typical MEMS device array comprise a large number of individual mechanical devices each electrically driven by multi-chip modules (MCMs). High density interconnection is achieved by mounting the MCMs mounted on both sides of a system interconnection substrate. Overall interconnection length is reduced by locating the MCMs in a common circuit driving a given mechanical element on opposite sides of the system interconnection substrate and interconnecting them using vias through the substrate. Rapid replacement/repair is facilitated by mounted all active elements in sockets using contact pin arrays for electrical connections. In service reliability is obtained by providing spare sockets for redundant MCMs.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: May 28, 2002
    Assignees: Agere Systems Guardian Corp., Lucent Technologies Inc.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, King Lien Tai
  • Patent number: 6370766
    Abstract: The specification describes methods for the manufacture of printed circuit cards which allow for final testing, including burn-in if required, of multiples of printed circuit cards as an integrated process panel prior to final packaging and singulation. This desired sequence of operations is made possible by the addition of arrays of test contacts at the edge of the integrated process panel where the test contacts can be accessed with an insertion test apparatus.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: April 16, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, Dean Paul Kossives, Yee Leng Low
  • Patent number: 6369444
    Abstract: The specification describes interconnection assemblies for silicon-on-silicon multichip modules. The silicon-on-silicon MCMs are mounted on epoxy/glass laminates which have a coefficient of thermal expansion (CTE) that essentially matches the CTE of silicon. In the preferred embodiment the assembly is a PC card with card edge connectors, i.e. without fixed solder interlevel interconnections, so that the CTE of the epoxy laminate comprising the card can be modified without regard to potential mismatch with a mother board.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: April 9, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, King Lien Tai
  • Patent number: 6342399
    Abstract: The specification describes a technique for burn-in electrical testing of IC dies prior to wire bonding the dies to the next interconnection level. The dies are provided with a test solder bump array interconnected to the IC contact pads of the dies. The Known Good Dies (KGD) can then be wire bonded, or alternatively flip-chip solder bump bonded, to the next interconnect level.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: January 29, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Yinon Degani
  • Patent number: 6282100
    Abstract: The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: August 28, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, Robert Charles Frye
  • Patent number: 6251705
    Abstract: The specification describes methods for manufacturing thin tiles for IC packages using thinning techniques. The method includes the step of thinning the IC devices in chip form. This is achieved at the final stage of assembly where the chips are flip-chip bonded to the substrate and the backside of the chips is exposed for thinning. Using this approach, final chip thickness of the order of 2-8 mils can be produced and overall package thickness is dramatically reduced.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: June 26, 2001
    Assignee: Agere Systems Inc.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, King Lien Tai
  • Patent number: 6232212
    Abstract: The specification describes techniques for applying solder bumps to IC chips. The solder bump sites are first provided with under bump metallization (UBM) for solder bump interconnections to the Al bonding sites on the IC chip. The substrate, i.e. the capping layer of the IC chip, is coated with photoresist and patterned to expose the UBM and a peripheral portion of the capping layer around the UBM. The solder paste is then applied and reflowed to form the solder bump. Since the photoresist hardens and becomes difficult to remove after the reflow step, a sacrificial buffer layer is interposed between the photoresist and the capping layer to facilitate removal of the photoresist without attacking the IC chip surface.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: May 15, 2001
    Assignee: Lucent Technologies
    Inventors: Yinon Degani, Dean Paul Kossives
  • Patent number: 6175158
    Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a silicon translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The thermal mismatch between the silicon translator and conventional printed wiring board materials is addressed by using an interposer which is essentially a ball grid array of plated-through holes that transfers the interconnect pattern from the translator to the printed wiring board. The interposer may have a composition with a coefficient of thermal expansion (CTE) that lies between the CTE of silicon and the CTE of the board material. It may also be provided with holes or slots for additional stress relief.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: January 16, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, Robert Charles Frye, King Lien Tai
  • Patent number: 6160715
    Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The translator also has a large area outboard of the IC chip area to allow fan out from high pin count chips to large pitch interconnection sites for interconnection to the next board level.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: December 12, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, Robert Charles Frye, King Lien Tai
  • Patent number: 6154370
    Abstract: The specification describes a recessed chip IC package in which the cavity in the printed wiring board into which the IC chip is recessed is used as a through hole interconnection, thus increasing the interconnection density. If the through cavity interconnections are used as power and ground the signal I/O pads and the signal runners are effectively isolated.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: November 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Robert Charles Frye, Yee Leng Low
  • Patent number: 6130141
    Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on IC chips with Al bonding sites. The UBM of the invention comprises a copper layer applied directly to the aluminum bonding sites. Reliable bonds are obtained if the Al surface is a nascent surface. Such a surface can be provided by back sputtering an aluminum bonding site, or by a freshly sputtered aluminum layer. The copper layer is deposited on the nascent aluminum surface in e.g. a cluster tool without breaking vacuum. The UBM can be patterned using subtractive techniques.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: October 10, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Jeffrey Alan Gregus
  • Patent number: 6100475
    Abstract: The specification describes techniques for attaching double sided circuit boards having plated through holes to interconnection substrates using solder bump arrays. The through holes are filled with a high melting point solder which allows solder bumps to be located directly on the through hole thus saving board area and reducing the interconnection length.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: August 8, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Yinon Degani, King Lien Tai
  • Patent number: 6077725
    Abstract: A multichip module is assembled using flip-chip bonding technology, a stencil printable solder paste and standard surface mount equipment for interconnecting signaling input/output contact pads on devices within such multichip module.
    Type: Grant
    Filed: September 3, 1992
    Date of Patent: June 20, 2000
    Assignee: Lucent Technologies Inc
    Inventors: Yinon Degani, Thomas Dixon Dudderar, King Lien Tai
  • Patent number: 6074897
    Abstract: A technique for enabling sufficient flow of flux cleaning fluids and an underfill material in the relatively low-profile gap between a flip-chip bonded IC chip and a substrate, such as a printed circuit board, is to provide at least one aperture in the substrate under the IC chip. The use of such an aperture enables, for example, flux cleaning fluid to flow through the aperture into the low-profile gap between the IC chip and the substrate surface, such as by the application of pressure or by gravity, which then exits through openings between formed interconnect bonds at a sufficient flow rate to adequately remove flux residues. An epoxy underfill to the IC chip can be formed in a similar manner. For example, a relatively thick bead of epoxy, such as on the order of the thickness of the IC chip, is deposited or stencil printed on the substrate surface around the edges of the IC chip and capillary action is then relied upon to draw the epoxy into the low-profile gap.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: June 13, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Lawrence Arnold Greenberg
  • Patent number: 6043670
    Abstract: The specification describes a technique for testing packaged or unpackaged IC devices in which the devices are aligned and placed onto a tacky layer of an anisotropic conductive medium (ACM). The tacky ACM layer provides the necessary electrical contact to the IC device while under test, and also preserves the alignment of the IC device during movement between stations. When electrical testing of the IC device is completed the IC device packages are lifted free of the tacky layer and permanently bonded to an interconnection substrate. In one embodiment the test interconnection substrate is a replica of the permanent interconnection substrate. In another mode of practicing the invention the test interconnection substrate is the actual permanent interconnection substrate, and the IC device is bonded in situ after electrical testing.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: March 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Alan Michael Lyons
  • Patent number: 6015652
    Abstract: The specification describes a process for applying under bump metallization (UBM) for solder bump interconnections on interconnection substrates. The process uses a lift-off technique for defining the UBM and the lift-off technique has improved edge definition as the result of radiation hardening of the photoresist after lithographic patterning.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: January 18, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Louis Nelson Ahlquist, Yinon Degani
  • Patent number: 6013877
    Abstract: The specification describes techniques for attaching double sided circuit boards having plated through holes to interconnection substrates using solder bump arrays. The through holes are filled with a high melting point solder which allows solder bumps to be located directly on the through hole thus saving board area and reducing the interconnection length.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: January 11, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, King Lien Tai
  • Patent number: 5990564
    Abstract: The specification describes an interconnect strategy for memory chip packages to reduce or eliminate alpha particle contamination from the use of high lead solder interconnections in the vicinity of semiconductor memory cells. In the primary embodiment a high tin solder is recommended. A multi-layer under bump metallization is described that is compatible with high tin solders and flip-chip solder bump technology.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: November 23, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Yinon Degani, Thomas Dixon Dudderar, King Lien Tai