Abstract: A circuit device includes: a first booster circuit, started by a predetermined input voltage, which converts the input voltage into a first boosted voltage higher than the input voltage; a capacitor, connected to the booster circuit, which charges the first boosted voltage; a second booster circuit, connected to the capacitor via a first switch element and started by a storage voltage in the capacitor, which converts the input voltage into a second boosted voltage higher than the first boosted voltage; and a second switch element which connects an output terminal of the second booster circuit with the capacitor. The first switch element turns on to start the second booster circuit so as to supply the storage voltage in the capacitor to the second booster circuit. After the second booster circuit has been started, the first switch element turns off to stop supplying the storage voltage.

Abstract: Heat from a circuit element is effectively conducted to a metal substrate so that reliability of a circuit apparatus is improved. A circuit element is configured such that a wiring layer is formed on a metal substrate. Power devices are mounted on the wiring layer in addition to a circuit element constituting a control unit. Steps are formed by grooves of a predetermined pattern on the primary surface of the metal substrate. High heat dissipation circuit elements generating a relatively large amount of heat (i.e., power devices) are mounted above projections on the metal substrate. Low heat dissipation circuit elements generating a relatively small amount of heat are mounted above the depression in the metal substrate.

Abstract: An electronic tuning system includes an electronic tuner for adjusting the predetermined control voltage of a voltage controlled oscillator (VCO) to tune the local frequency signal to radio waves on an arbitrary channel in accordance with channel selection information. A booster circuit boosts a source voltage to generate a boosted voltage in order to ensure the predetermined control voltage. A non-volatile memory stores the channel selection information in response to a predetermined write voltage. The boosted voltage of the booster circuit is utilized as the predetermined write voltage.

Abstract: A circuit device includes a metal substrate; and a plurality of circuit elements, mounted on the metal substrate, which electrically connects to the metal substrate. The metal substrate is made of a copper plate of high thermal conductivity. The metal substrate is demarcated into a plurality of sections by insulating films added with a filler for enhancing the thermal conductivity in resin. The circuit elements, which have respective independent operating potentials on a side of the metal substrate of the circuit elements, are respectively provided on separated copper plates.

Abstract: A set of voltage output units outputs the light intensity detected by a photodetection device in the form of a voltage value. With the set of voltage output units, the capacitance of the cathode terminal of a photodiode PD provided within the pixel is charged or discharged using the photoelectric current. A current output unit outputs photoelectric current Iph flowing from the photodetection device. The current output unit includes a current output transistor provided between one terminal of the photodetection device and the data line. A pixel circuit effects control of the pixel so as to activate either the set of the voltage output units or the current output unit, thereby outputting either voltage value or photoelectric current to the data line connected to the pixel.

Abstract: A semiconductor memory device capable of suppressing size increase and reducing the operating time is provided. This semiconductor memory device comprises storage portion, connected to a data read line, containing a material having a hysteresis property and data read portion connected to the data read line for reading data stored in the storage portion, for supplying prescribed energy capable of changing a storage state of the storage portion from an initial state supplying no prescribed energy and thereafter returning the intensity of the energy to a level not changing the storage state for reading the data with the data read portion on the basis of the current state of the data read line and the state of the data read line in the initial state in data reading.

Abstract: In a digital-to-analog (D-A) converter, a plurality of respectively weighted capacitances are configured such that one ends of them are connected to an input terminal of a comparator and the other ends of them are connected to a power supply line or ground line. A plurality of switches selectively connect the other ends of corresponding capacitances with the power supply line or ground line. A possible range of capacitance division ratio in the plurality of capacitances is set in a manner that the magnitude and position of an output voltage range of the D-A converter is set to a desired value within a voltage range between power supply voltage and ground potential.

Abstract: A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

Abstract: A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

Abstract: A memory device capable of suppressing reduction of a read margin resulting from fluctuation of a reference potential while reducing the area of a memory cell array is obtained. This memory device comprises hysteretic capacitance device and a read circuit applying a bias voltage to the capacitance means in different directions in a first time and a second time of data reading respectively for defining read data by comparing first read data and second read data with each other.

Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.

Abstract: A semiconductor memory device having a first memory including a bit line, a word line arranged to intersect with the bit line and a storage unit arranged between the bit line and the word line, and a second memory different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate in a stacked manner reducing the thickness in the height direction and attaining further miniaturization (thinning). Further, no wire having a large parasitic capacitance or solder is employed for connecting the first memory and the second memory, thereby enabling high-speed data transfer between the first memory and the second memory.

Abstract: A semiconductor memory device capable of suppressing size increase and reducing the operating time is provided. This semiconductor memory device comprises storage portion, connected to a data read line, containing a material having a hysteresis property and data read portion connected to the data read line for reading data stored in the storage portion, for supplying prescribed energy capable of changing a storage state of the storage portion from an initial state supplying no prescribed energy and thereafter returning the intensity of the energy to a level not changing the storage state for reading the data with the data read portion on the basis of the current state of the data read line and the state of the data read line in the initial state in data reading.

Abstract: A memory capable of suppressing disturbance is provided. This memory comprises a bit line, a word line arranged to intersect with the bit line and first storage means connected between the bit line and the word line, and applies prescribed reverse voltages to at least non-selected first storage means connected to a non-selected word line substantially identical times respectively or substantially applies no voltage through a read operation and a rewrite operation.

Abstract: A semiconductor memory device including different types of memories capable of attaining further miniaturization (thinning) and speed-up. This semiconductor memory device comprises a first memory including a bit line, a word line arranged to intersect with the bit line and storage means (43) arranged between the bit line and the word line and a second memory (13) different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate (31). When forming the first memory and the second memory on the same semiconductor substrate (31) in a stacked manner in this case, the thickness in the height direction is reduced, whereby further miniaturization (thinning) can be attained. Further, no wire having a large parasitic capacitance or solder may be employed for connection of the first memory and the second memory, whereby high-speed data transfer is enabled between the first memory and the second memory.

Abstract: A memory device capable of suppressing reduction of a read margin resulting from fluctuation of a reference potential while reducing the area of a memory cell array is obtained. This memory device comprises hysteretic capacitance means and a read circuit applying a bias voltage to the capacitance means in different directions in a first time and a second time of data reading respectively for defining read data by comparing first read data and second read data with each other.

Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell is provided. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a diode, arranged between the bit line and the word line, including a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.

Abstract: An electronic tuning system includes an electronic tuner for adjusting the predetermined control voltage of a voltage controlled oscillator (VCO) to tune the local frequency signal to radio waves on an arbitrary channel in accordance with channel selection information. A booster circuit boosts a source voltage to generate a boosted voltage in order to ensure the predetermined control voltage. A non-volatile memory stores the channel selection information in response to a predetermined write voltage. The boosted voltage of the booster circuit is utilized as the predetermined write voltage.

Abstract: In a charge pump type booster circuit, a capacitance coupling is performed between each capacitor of a charge pump series and each capacitor of another charge pump series by an equalizer, and a discharge current of the capacitors of one charge pump series is used as a charging current for the capacitors of the other charge pump series. Thereafter, each capacitor in each charge pump series is subjected to a generally high or low potential coupling by a driver circuit. As a result, the sum of charge/discharge currents of the capacitors in each charge pump series can be half as much as compared to when a single charge pump type booster circuit is provided. Even when a number n of stages of the charge pump series is increased, the power consumption can be reduced.

Abstract: A flash EEPROM has a memory cell array of memory cells. Each memory cell includes a floating gate electrode, a source, a drain and a control gate electrode. A data value is stored in a memory cell by storing a charge in its floating gate electrode. A control circuit controls voltages applied to the control gate electrode, the source and the drain of the memory cells. A charge which is greater than a charge amount corresponding to a desired data value is stored in the floating gate electrode of a memory cell. In the write mode, charge is drained from the floating gate electrode. A write determining circuit checks the amount of charge remaining in the floating gate electrode after charge has been drained from it. The write determining circuit disables the write operation when the amount of charge remaining in the floating gate electrode reaches the charge amount corresponding to the desired data value.