Abstract: A semiconductor memory device is described that has an improved read characteristics. The semiconductor memory device includes a plurality of memory cells, a reference cell, a comparator located between the memory cells and the reference cell, and a discriminator coupled to the comparator. The comparator compares the actual signal equivalent to a value of a current flowing in each of the memory cells and reference signals equivalent to a value of a current flowing in the reference cell with each other to output a comparison result signal in each of data reading operation modes. The discriminator discriminates a value of data stored in each of the memory cells based on the comparison result signal. The discriminator includes a circuit shared for discrimination of a data value in each of the data reading operation modes.

Abstract: A non-volatile semiconductor memory device includes a plurality of memory cells. Each of the plurality of memory cells has a control gate, a source, a drain and a floating gate for storing charges. The floating gate is preferably capacitively coupled to at least one of the source and the drain. The memory device also includes a control circuit for controlling voltages that are respectively applied to the control gate, the source and the drain in order to execute an erasure operation of at least one memory cell in a "memory cell-by-memory cell" format.

Abstract: A non-volatile semiconductor memory device that accurately writes and reads multivalue data to and from memory cells includes a control unit and a plurality of memory cells each having a control gate, a source, a drain and a floating gate. The floating gate has an electric potential controllable by applying predetermined voltages to the control gate, the source and the drain. The control unit controls the electric potential of the floating gate to write predetermined data in the memory cells. The predetermined data corresponds to one of a plurality of preset electric potential ranges of the floating gate. The electric potential of the floating gate is controlled to lie in one of the plurality of electric potential ranges of the floating gate corresponding to the predetermined data. Each of the memory cells is activatable when the floating gate has either a higher potential or a lower potential than a predetermined electric potential.

Abstract: A semiconductor memory unit that includes a regular memory cell array and a redundant column which utilize common rows for actuating regular memory cells when defective memory cells are detected. A first access device designates a column in the regular memory cell array which corresponds to a externally designated column address. A second access device designates a redundant column which corresponds to the externally designated column address. When the regular memory cell array contains defective memory cells and the column addresses of their cells coincide with the externally designated column address, a validating device validates the access to the redundant column by means of the second access device. When the regular memory cell array contains defective memory cells having column addresses other than that designated externally, the validating device validates the access to the column in the regular memory cell array by means of the first access device.