Patents by Inventor Yohei Yamaguchi
Yohei Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11810921Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.Type: GrantFiled: November 9, 2022Date of Patent: November 7, 2023Assignee: Japan Display Inc.Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
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Patent number: 11764233Abstract: A display device including a substrate having thin film transistors (TFT) comprising: the TFT including an oxide semiconductor film, a gate electrode and an insulating film formed between the oxide semiconductor film and the gate electrode, wherein a first aluminum oxide film and a second aluminum oxide film, which is formed on the first aluminum oxide film, are formed between the insulating film and the gate electrode, an oxygen concentration in the first aluminum oxide film is bigger than an oxygen concentration in the second aluminum oxide film.Type: GrantFiled: August 27, 2021Date of Patent: September 19, 2023Assignee: Japan Display Inc.Inventors: Hajime Watakabe, Isao Suzumura, Akihiro Hanada, Yohei Yamaguchi
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Patent number: 11764305Abstract: A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.Type: GrantFiled: October 26, 2021Date of Patent: September 19, 2023Assignee: Japan Display Inc.Inventors: Yohei Yamaguchi, Yuichiro Hanyu, Hiroki Hidaka
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Publication number: 20230271290Abstract: The present invention includes a plurality of protective bodies (13, 14, 15) sequentially connected in a moving direction of a moving body and separating a movement path of the moving body from the outside. The protective body (15) at a first end is connected to a predetermined end (12a) of an area to be protected, and the protective body (13) at a second end is connected to the moving body. The plurality of protective bodies (13, 14, 15) are configured to be expanded and contracted as a whole by movement of the moving body. A structural body (35) having a groove (35a) having a top opening and forming a flow path is provided. The structural body (35) is arranged along the protective bodies (13, 14, 15) below the protective bodies (13, 14, 15) or arranged along the protective bodies (13, 14, 15) such that the lower ends of the protective bodies (13, 14, 15) are inserted in the groove (35a) through the top opening of the groove (35a).Type: ApplicationFiled: June 22, 2021Publication date: August 31, 2023Applicant: DMG MORI CO., LTD.Inventors: Futoshi YAMAZAKI, Yohei YAMAGUCHI, Keisuke TAKAHASHI
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Patent number: 11742430Abstract: The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.Type: GrantFiled: June 15, 2021Date of Patent: August 29, 2023Assignee: Japan Display Inc.Inventors: Yohei Yamaguchi, Kazufumi Watabe, Tomoyuki Ariyoshi, Osamu Karikome, Ryohei Takaya
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Patent number: 11694482Abstract: An information processing device includes a receiving unit for receiving face image data of a student, who takes a class in a classroom, a plurality of times during the class from a camera provided in the classroom; a control unit for comparing the face image data with registered face image data of the student and count the number of times the student of the registered face image data is photographed by the camera during the class; and a transmission unit for transmitting the number of times of photographing to a terminal device used by a teacher who teaches the class.Type: GrantFiled: July 17, 2020Date of Patent: July 4, 2023Assignee: I-PRO CO., LTD.Inventors: Takashi Kamio, Ryo Kitamura, Michito Hirose, Yohei Yamaguchi
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Publication number: 20230167232Abstract: This polyethylene furanoate has an intrinsic viscosity of 0.95 - 1.50 dl/g. Said intrinsic viscosity is measured (the Huggins constant is defined as 0.32) at 30° C. by using an Ubbelohde viscometer, after dissolving 0.25 g of the polyethylene furanoate in 50 ml of a solvent mixture of phenol/1,1,2,2-tetrachloroethane = 50/50 (weight ratio).Type: ApplicationFiled: December 28, 2022Publication date: June 1, 2023Applicants: KIRIN HOLDINGS KABUSHIKI KAISHA, Mitsubishi Chemical CorporationInventors: Takashi SATO, Satoshi KATO, Rie SHIRAHAMA, Takafumi ASAKURA, Masaki NAKAYA, Yohei YAMAGUCHI
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Publication number: 20230081420Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.Type: ApplicationFiled: November 9, 2022Publication date: March 16, 2023Inventors: Isao SUZUMURA, Kazufumi WATABE, Yoshinori ISHII, Hidekazu MIYAKE, Yohei YAMAGUCHI
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Publication number: 20230027596Abstract: A wiring structure includes a structure body including a pattern, a first conductive layer above the structure body, the first conductive layer having a shape, the shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body, a first insulating layer above the first conductive layer, the first insulating layer having a first opening overlapping the edge of the pattern of the structure body in a plane view, and r is arranged with a second opening in a region overlapping the semiconductor layer in a plane view, a second conductive layer in the first opening, the second conductive layer being connected to the first conductive layer.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Inventor: Yohei YAMAGUCHI
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Publication number: 20230017133Abstract: RC-network components that include a substrate having a capacitor with a thin-film top electrode portion at a surface at one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance in series with the capacitor is controlled by providing a contact plate, spaced from the top electrode portion by an insulating layer, and a set of one or more bridging contacts in openings in the insulating layer. The bridging contacts electrically interconnect the top electrode portion and contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. Temperature concentration at the periphery of the openings is reduced by providing reduced thickness portions in the insulating layer around the periphery of the openings.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Yohei YAMAGUCHI, Yasuhiro MURASE, Stéphane BOUVIER
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Publication number: 20230020074Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Applicant: Japan Display Inc.Inventors: Yohei YAMAGUCHI, Arichika ISHIDA, Hidekazu MIYAKE, Hiroto MIYAKE, Isao SUZUMURA
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Publication number: 20230010467Abstract: RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.Type: ApplicationFiled: September 15, 2022Publication date: January 12, 2023Applicant: Murata Manufacturing Co., Ltd.Inventors: Yohei YAMAGUCHI, Yasuhiro MURASE, Stéphane BOUVIER
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Publication number: 20220389269Abstract: Provided is a hard coating film for foldable displays that does not form creases or cracks in the folding portion, and that is also excellent in reducing iridescent colors (interference mottling) caused by fine cracks in an easy-to-adhere resin layer or other layers. The hard coating film for foldable displays contains a polyester film having a thickness of 10 to 80 ?m, an easy-to-adhere resin layer, and a hard coating layer, the easy-to-adhere resin layer and the hard coating layer being stacked in this order on at least one surface of the polyester film, wherein the easy-to-adhere resin layer is a cured product of a composition containing at least one compound selected from the group consisting of titanium compounds and zirconium compounds and a polyester resin, and the polyester film having the easy-to-adhere resin layer stacked thereon but not yet having the hard coating layer stacked thereon satisfies characteristics within specific ranges.Type: ApplicationFiled: June 30, 2020Publication date: December 8, 2022Applicant: TOYOBO CO., LTD.Inventors: Yohei YAMAGUCHI, Kokichi TOKUO, Shotaro NISHIO, Kiwamu KAWAI
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Patent number: 11521990Abstract: The object of the present invention is to make it possible to form an LTPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first. TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.Type: GrantFiled: June 2, 2021Date of Patent: December 6, 2022Assignee: Japan Display Inc.Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
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Publication number: 20220375967Abstract: The purpose of the present invention is to improve reliability of the TFT of the oxide semiconductor. The feature of the invention is: A display device comprising: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor, a first gate insulating film is formed under the first oxide semiconductor, a first gate electrode is formed under the first gate insulating film, an interlayer insulating film is formed on the first oxide semiconductor; a drain wiring, which connects with the first oxide semiconductor, and a source wiring, which connects with the first oxide semiconductor, are formed on the interlayer insulating film; the drain wiring or the source wiring is a laminated structure of a second oxide semiconductor and a first metal, the second oxide semiconductor is under the first metal.Type: ApplicationFiled: June 3, 2022Publication date: November 24, 2022Applicant: Japan Display Inc.Inventor: Yohei YAMAGUCHI
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Publication number: 20220376009Abstract: A semiconductor device includes an insulating substrate, a first semiconductor region configured of polysilicon formed on the insulating substrate, an insulating film laminated on the first semiconductor region, a contact hole formed in the insulating film and reaching the first semiconductor region, a second semiconductor region configured of an oxide semiconductor formed on the insulating film, a contact electrode configured of a conductive material and electrically connected to the first semiconductor region, where the conductive material is embedded in the contact hole. The insulating film contains a metallic element at an interface with the contact hole, where the metallic element forms the oxide semiconductor.Type: ApplicationFiled: August 3, 2022Publication date: November 24, 2022Inventor: Yohei YAMAGUCHI
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Patent number: 11488984Abstract: A wiring structure includes a structure body including a pattern, a first conductive layer above the structure body, the first conductive layer having a shape, the shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body, a first insulating layer above the first conductive layer, the first insulating layer having a first opening overlapping the edge of the pattern of the structure body in a plane view, and r is arranged with a second opening in a region overlapping the semiconductor layer in a plane view, a second conductive layer in the first opening, the second conductive layer being connected to the first conductive layer.Type: GrantFiled: January 3, 2020Date of Patent: November 1, 2022Assignee: Japan Display Inc.Inventor: Yohei Yamaguchi
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Patent number: 11474406Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.Type: GrantFiled: December 18, 2020Date of Patent: October 18, 2022Assignee: Japan Display Inc.Inventors: Yohei Yamaguchi, Arichika Ishida, Hidekazu Miyake, Hiroto Miyake, Isao Suzumura
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Publication number: 20220275159Abstract: Provided is a hard coating film for foldable displays that does not form creases or cracks in the folding portion, and that is also excellent in reducing iridescent colors (interference mottling) caused by fine cracks in an easy-to-adhere resin layer or other layers.Type: ApplicationFiled: June 30, 2020Publication date: September 1, 2022Applicant: TOYOBO CO., LTD.Inventors: Yohei YAMAGUCHI, Kokichi TOKUO, Shotaro NISHIO, Kiwamu KAWAI
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Publication number: 20220262825Abstract: The purpose of the invention is to form a stable oxide semiconductor TFT in a display device. The concrete structure is: A display device having a TFT substrate that includes a TET having an oxide semiconductor layer comprising: the oxide semiconductor layer is formed on a first insulating film that is formed by a silicon oxide layer, the oxide semiconductor layer and an aluminum oxide film are directly formed on the first insulating film. The first insulating film becomes oxygen rich when the aluminum oxide film is formed on the first insulating film by sputtering. Oxygens in the first insulating film is effectively confined in the first insulating film, eventually, the oxygens diffuse to the oxide semiconductor for a stable operation of the oxide semiconductor TET.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Applicant: Japan Display Inc.Inventor: Yohei YAMAGUCHI