Abstract: A memory device includes: insulator layers spaced apart from one another in a first direction; conductor layers spaced apart from one another in the first direction, the insulator layers and the insulator layers alternately arranged along the first direction; and a memory pillar extending in the first direction to intersect the conductor layers. The conductor layers include a first conductor layer having a first portion and a second portion in contact with the memory pillar. The first portion is recessed relative to the second portion in a second direction intersecting the first direction.

Abstract: A semiconductor storage device includes a first word line, a first insulating layer extending along the first word line, a first memory cell connected to the first word line, a second memory cell connected to the first word line, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, and a control circuit. The second memory cell is farther from the first insulating layer than the first memory cell. The control circuit is configured to apply a first voltage to the first bit line during a read operation of the first memory cell, and apply a second voltage to the second bit line during a read operation of the second memory cell. The second voltage is higher than the first voltage.

Abstract: According to one embodiment, a semiconductor memory device includes first conductive layers stacked on a substrate at a first pitch, second conductive layers stacked on the substrate at a second pitch, and third conductive layers stacked on the substrate at a third pitch. The third conductive layers are between the substrate and the second conductive layers in a first direction. A semiconductor layer extends in the first direction through the first conductive layers, the second conductive layers, and the third conductive layers. The semiconductor layer has a first portion facing the first conductive layers and the second conductive layers and a second portion facing the third conductive layers. The second pitch is greater than the first pitch and the third pitch.

Abstract: A semiconductor storage device includes first and second stacked bodies, a first semiconductor layer, a first charge storage layer, a conductive layer, and a first silicon oxide layer. The first stacked body includes first insulation layers and first gate electrode layers that are alternately stacked in a first direction. The first semiconductor layer extends in the first stacked body in the first direction. The first charge storage layer is provided between the first semiconductor layer and the first gate electrode layers. The conductive layer is provided between the first stacked body and the second stacked body and extends in the first direction and a second direction. The first silicon oxide layer is provided between the conductive layer and the first gate electrode layers. The first silicon oxide layer containing an impurity being at least one of phosphorus, boron, carbon, and fluorine.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.

Abstract: A memory device includes a semiconductor layer including adjacent cell and non-cell areas in a first direction, first and second conductive lines on the layer, extending along the first direction and arranged away from each other in a second direction crossing the first direction, conductor layers arranged above the semiconductor layer in a third direction crossing the first and second directions, pillars on the cell area, passing through the conductor layers in the third direction and forming memories at intersections with the conductor layers, and shunt lines extending along the second direction and arranged in the first direction above the cell area, each of the shunt lines connected to the first and second lines via third conductive lines. A length between the shunt line closest to the non-cell area and a boundary between the cell and non-cell areas is less than a length between adjacent shunt lines.

Abstract: According to one embodiment, in a semiconductor storage device, the first contact plug electrically connects the third region to the first drive circuit. The second contact plug is provided on one end side of a fourth region in the third direction, the fourth region arranged between the first separation film and the second separation film in the second conductive layer. The second contact plug electrically connects the fourth region to the first drive circuit. The third contact plug is provided on the other end side of the third region in the third direction. The third contact plug electrically connects the third region to the second drive circuit.

Abstract: A semiconductor storage device includes first and second stacked bodies, a first semiconductor layer, a first charge storage layer, a conductive layer, and a first silicon oxide layer. The first stacked body includes first insulation layers and first gate electrode layers that are alternately stacked in a first direction. The first semiconductor layer extends in the first stacked body in the first direction. The first charge storage layer is provided between the first semiconductor layer and the first gate electrode layers. The conductive layer is provided between the first stacked body and the second stacked body and extends in the first direction and a second direction. The first silicon oxide layer is provided between the conductive layer and the first gate electrode layers. The first silicon oxide layer containing an impurity being at least one of phosphorus, boron, carbon, and fluorine.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, first and second word lines, and a bit line. The first and second memory cells are coupled to each other and adjacent to each other. When a state of the second memory cell is the first state or one of the states corresponding to a lower threshold voltage distribution than that of the first state, the first memory cell data is read in a first period during which a first voltage is applied to the second word line. And when the state of the second memory cell is the second state or one of the states corresponding to a higher threshold voltage distribution than the second state, the first memory cell data is read in a second period during which a second voltage higher than the first voltage is applied to the second word line.

Abstract: According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.

Abstract: A memory device includes a semiconductor layer including adjacent cell and non-cell areas in a first direction, first and second conductive lines on the layer, extending along the first direction and arranged away from the first line in a second direction crossing the first direction, conductor layers arranged above the semiconductor layer in a third direction crossing the first and second directions, pillars on the cell area, passing through the conductor layers in the third direction and forming a memory at an intersection with each conductor layer, and shunt lines extending along the second direction and arranged in the first direction above the cell area, each of the shunt lines connected to the first and second lines via third conductive lines. A length between the shunt line closest to the non-cell area and a boundary between the cell and non-cell areas is less than a length between adjacent shunt lines.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.

Abstract: A semiconductor device includes a base, a stacked body, a plate-shaped portion, and first to third columnar portions. The stacked body is provided over the base. The plate-shaped portion is inside the stacked body from an upper end of the stacked body to the base. The first to third columnar portions are inside the stacked body from the upper end of the stacked body to the base. The second columnar portion is located away from the first columnar portion in a first direction. The third columnar portion is aligned with the first columnar portion and the second columnar portion in the first direction. A pitch between the third columnar portion and the first columnar portion is a first pitch. A pitch between the third columnar portion and the second columnar portion is a second pitch larger than the first pitch.

Abstract: According to one embodiment, in a semiconductor storage device, the first contact plug electrically connects the third region to the first drive circuit. The second contact plug is provided on one end side of a fourth region in the third direction, the fourth region arranged between the first separation film and the second separation film in the second conductive layer. The second contact plug electrically connects the fourth region to the first drive circuit. The third contact plug is provided on the other end side of the third region in the third direction. The third contact plug electrically connects the third region to the second drive circuit.

Abstract: According to one embodiment, in a semiconductor storage device, a peripheral circuit supplies a first voltage to a second region when supplying a select potential to a region corresponding to the second region, in a second conductive layer. The peripheral circuit supplies a second voltage higher than the first voltage to a first region when supplying a select potential to a region corresponding to the first region, in the second conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.

Abstract: A semiconductor device includes a base, a stacked body, a plate-shaped portion, and first to third columnar portions. The stacked body is provided over the base. The plate-shaped portion is inside the stacked body from an upper end of the stacked body to the base. The first to third columnar portions are inside the stacked body from the upper end of the stacked body to the base. The second columnar portion is located away from the first columnar portion in a first direction. The third columnar portion is aligned with the first columnar portion and the second columnar portion in the first direction. A pitch between the third columnar portion and the first columnar portion is a first pitch. A pitch between the third columnar portion and the second columnar portion is a second pitch larger than the first pitch.

Abstract: A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. Each memory cell includes a charge retention film between the semiconductor channel and a respective word line in the plurality of word lines. A controller is connected to the semiconductor channel and the word lines and configured to apply a program voltage during a program operation to a memory cell at a potential that increases in voltage steps, and a voltage increment between the voltage steps decreases during the program operation. The increment voltage is changed by the controller depending on a position of the memory cell along the semiconductor channel in the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory string including first and second select transistors and memory cell transistors; a bit line connected to the first select transistor; word lines which are connected to gates of the memory cell transistors, respectively; first and second select gate lines which are connected to gates of the first and second select transistors, respectively; a first contact plug connected to the first select gate line; a first wiring layer provided on the first contact plug; a second contact plug connected to the second select gate line; a second wiring layer provided on the second contact plug; and a row decoder connected to the first and second wiring layers. The row decoder applies different voltages to the first select gate line and the second select gate line.