Abstract: A semiconductor storage device includes a memory cell array, and a control circuit. The memory cell array has memory cells including variable resistive elements disposed at intersections of a plurality of first lines and a plurality of second lines. The control circuit performs a set pulse applying operation, and a cure pulse applying operation. The set pulse applying operation applies a set pulse to a variable resistive element so as to cause the variable resistive element to transition from a high resistance state to a low resistance state. The cure pulse applying operation applies a cure pulse to the variable resistive element. The cure pulse has a polarity that is opposite of a polarity of the set pulse, and is larger than the set pulse.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.

Abstract: This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.

Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array including memory cells, each of the memory cells disposed at each of intersections of first lines and second lines and including a variable resistor; and a control circuit configured to apply a first voltage to a selected first line and to apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, such that a selected memory cell is applied with a first potential difference required in an operation of the selected memory cell. The control circuit is configured such that when the first potential difference is applied a plurality of times to a plurality of the selected memory cells to execute the operation, the number of selected memory cells simultaneously applied with the first potential difference can be changed.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including first lines, second lines, and memory cells provided at each of intersections of the first lines and the second lines; and a control unit including a row control circuit, a first column control circuit provided on a side of one ends of the second lines, and a second column control circuit provided on a side of the other ends of the second lines, the control unit, during an access operation, controlling a potential of the first lines and the second lines such that a bias, which is lower than that applied to a certain unselected memory cell, is applied to those of unselected memory cells that are located more toward a center of the memory cell array in the column direction than the certain unselected memory cell.

Abstract: According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.

Abstract: A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.

Abstract: According to one embodiment, a non-volatile memory device includes: a plurality of first interconnects, and each of the first interconnects extending in a first direction; a plurality of second interconnects, and each of the second interconnects extending in a second direction intersecting with the first direction; a memory cell connected between each of the plurality of first interconnects and each of the plurality of second interconnects, the memory cell including a memory layer and a diode connected to the memory layer; and a control circuit capable of selecting a selection first interconnect among the first interconnects, selecting a selection second interconnect among the second interconnects, and selecting a selection memory cell connected to both the selection first interconnect and the selection second interconnect.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.

Abstract: In a memory cell array, memory cells each including a variable resistance element are arranged at crossing portions between a plurality of first wiring and a plurality of second wirings. A control circuit executes a set operation, a reset operation, and a training operation. In the set operation, a set pulse is applied to the variable resistance element to change the variable resistance element from a high resistance state to a low resistance state. In the reset operation, a reset pulse having an opposite polarity to the polarity of the set pulse is applied to the variable resistance element to change the variable resistance element from the low resistance state to the high resistance state. In the training operation, the set pulse and the reset pulse are continuously applied to the variable resistance element.

Abstract: According to one embodiment, a nonvolatile memory device includes: a memory cell array including first wirings, second wirings, and a memory cell connected between the first wirings and the second wirings; and a control circuit unit configured to select a selected memory cell from the memory cells, perform a first operation of changing a resistance state of the selected memory cell between a first resistance state and a second resistance state, and determine whether the first operation has been properly performed or not and perform retry operation such as applying a retry pulse when the first operation has not been properly performed. The control circuit unit regards the selected memory cell as excessive retry operation and inhibits the selected memory cell in accordance with the number of times of the excessive retry operation when the number of times of the retry operation is over k times.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of memory cells, a plurality of wires, and a control circuit. The control circuit allows a first current to change a state to flow on a selected cell by applying a first potential difference between a pair of wires that sandwich the selected cell selected from the plurality of memory cells with respect to the semiconductor substrate vertically, and allows a second current lower than the first current to flow on an non-selected cell in the same direction as the direction of the first current by applying a second potential difference between a pair of wires that sandwich the non-selected cell connected to a wire shared with the selected cell on a different layer from the selected cell.

Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines; and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.

Abstract: A control circuit is configured to perform a state determination operation to sense voltages of a plurality of first wiring lines, the voltages changing based on current flowing from the first wiring lines to a plurality of second wiring lines via a plurality of variable resistive elements. Then, the control circuit is configured to adjust voltages to be applied to the first and second wiring lines in a reset operation or a set operation based on the voltages of the first wiring lines sensed in the state determination operation.

Abstract: A memory cell array comprises memory cells disposed at intersections of a plurality of first lines disposed in parallel and a plurality of second lines disposed intersecting the first lines. The memory cell includes a variable resistance element. A set operation-dedicated first driver circuit, when executing on the memory cell a set operation for switching a memory cell from a high-resistance state to a low-resistance state, supplies a voltage to the first lines. A reset operation-dedicated first driver circuit, when executing on the memory cell a reset operation for switching the memory cell from a low-resistance state to a high-resistance state, supplies a voltage to the first lines. A length of a wiring line between the set operation-dedicated first driver circuit and the memory cell array is longer compared to a length of a wiring line between the reset operation-dedicated first driver circuit and the memory cell array.

Abstract: A control circuit is configured to perform, when a plurality of variable resistance elements connected to a selected first wiring line are selected, a read operation to sense a voltage of the selected first wiring line. The control circuit is configured to adjust, according to the voltage of the selected first wiring line sensed in the read operation, a voltage to be applied to the selected first wiring line in a reset operation or a set operation. The reset operation is an operation to increase resistance of a variable resistance element. The set operation is an operation to decrease resistance of a variable resistance element.

Abstract: A memory cell array includes memory cells disposed at intersections of first lines and second lines, and each having a rectifying element and a variable resistance element connected in series. A control circuit, when performing an operation to change retained data, applies a first voltage to a selected first line and applies a second voltage to a selected second line; furthermore, applies a third voltage to a non-selected first line; and, moreover, applies a fourth voltage larger than the third voltage to a non-selected second line. An absolute value of a difference between the third voltage and the fourth voltage is set smaller than an absolute value of a difference between the first voltage and the second voltage by an amount of an offset voltage. A value of the offset voltage increases as the absolute value of the difference between the first and second voltages increases.

Abstract: A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.