Abstract: A memory device includes stacked word lines stacked and a semiconductor channel passing through the word lines in a first direction. Memory cells are disposed along the semiconductor channel in the first direction. Each memory cell includes a charge retention film between the semiconductor channel and a respective word line in the plurality of word lines. A controller is connected to the semiconductor channel and the word lines and configured to apply a program voltage during a program operation to a memory cell at a potential that increases in voltage steps, and a voltage increment between the voltage steps decreases during the program operation. The increment voltage is changed by the controller depending on a position of the memory cell along the semiconductor channel in the first direction.

Abstract: A semiconductor memory device includes a stacked body, a first semiconductor member, a first insulating layer, a second semiconductor member, and a second insulating layer. The stacked body includes an electrode film and an insulating film arranged alternately along a first direction. The first and second semiconductor members extend in the first direction and pierce the electrode film and the insulating film. The first insulating layer contacts the insulating film and is provided at a periphery of the first semiconductor member. The second insulating layer contacts the insulating film and is provided at a periphery of the second semiconductor member. The first insulating layer is thicker than the second insulating layer. A major diameter of the first semiconductor member is smaller than a major diameter of the second semiconductor member when viewed from the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes first to fourth conductive layers, a first intermediate insulating layer, a second intermediate insulating layer, an inter-layer insulating layer, a first semiconductor body, a first memory layer, a second semiconductor body, a second memory layer, and a first interconnect. The second conductive layer is separated from the first conductive layer in a first direction. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction. The fourth conductive layer is separated from the third conductive layer in the first direction and arranged with the second conductive layer in the second direction. The first intermediate insulating layer is provided between the first conductive layer and the third conductive layer. The second intermediate insulating layer is provided between the second conductive layer and the fourth conductive layer.

Abstract: The semiconductor device includes memory strings, word lines, bit lines and a circuit. The memory strings each include memory cells connected in series. The gate electrode surrounds the channel. The word lines are electrically connected to gate electrodes of memory cells. The bit lines are electrically connected to ends of current paths in the memory strings respectively. The circuit controls a program operation of information. The information includes at least three of a first, a second and a third levels or more corresponding to threshold voltages of the memory cells. When starting the program operation, the circuit applies a program selection voltage to channels of memory cells to be programmed at the second level, and a program suppression voltage to channels of memory cells maintaining the first level and channels of memory cells to be programmed at the third level.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.

Abstract: A semiconductor memory device according to an embodiment comprises a stacked body, the stacked body including a plurality of conductive layers disposed on a semiconductor substrate and an inter-layer insulating film disposed between the plurality of conductive layers. A columnar semiconductor layer is surrounded as a stacking direction of the stacked body. An isolation film extends from an outer surface of the stacked body to a bottom of the stacked body and has a longitudinal direction in a second direction. At least some of the isolation films include a base portion extending in the second direction and a terminal portion positioned at an end of the base portion, and a width of the end in a third direction intersecting the second direction is larger than a width of the base portion.

Abstract: This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.

Abstract: A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.

Abstract: According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.

Abstract: First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.

Abstract: A semiconductor memory device has a memory cell array including memory cells, the memory cell being disposed at an intersection of first lines and second lines, the second lines being disposed intersecting the first lines, and the memory cell including a variable resistance element; and a control circuit. The control circuit is configured to execute a forming operation sequentially on a plurality of the memory cells. The control circuit applies a forming voltage to a selected memory cell of the memory cells, and controls the forming voltage such that the forming voltage is lower as the forming operation progresses.

Abstract: A control circuit is configured to perform a state determination operation to sense voltages of a plurality of first wiring lines, the voltages changing based on current flowing from the first wiring lines to a plurality of second wiring lines via a plurality of variable resistive elements. Then, the control circuit is configured to adjust voltages to be applied to the first and second wiring lines in a reset operation or a set operation based on the voltages of the first wiring lines sensed in the state determination operation.

Abstract: A memory cell array comprises memory cells disposed at intersections of a plurality of first lines disposed in parallel and a plurality of second lines disposed intersecting the first lines. The memory cell includes a variable resistance element. A set operation-dedicated first driver circuit, when executing on the memory cell a set operation for switching a memory cell from a high-resistance state to a low-resistance state, supplies a voltage to the first lines. A reset operation-dedicated first driver circuit, when executing on the memory cell a reset operation for switching the memory cell from a low-resistance state to a high-resistance state, supplies a voltage to the first lines. A length of a wiring line between the set operation-dedicated first driver circuit and the memory cell array is longer compared to a length of a wiring line between the reset operation-dedicated first driver circuit and the memory cell array.

Abstract: According to one embodiment, a nonvolatile memory device includes: a memory cell array including first wirings, second wirings, and a memory cell connected between the first wirings and the second wirings; and a control circuit unit configured to select a selected memory cell from the memory cells, perform a first operation of changing a resistance state of the selected memory cell between a first resistance state and a second resistance state, and determine whether the first operation has been properly performed or not and perform retry operation such as applying a retry pulse when the first operation has not been properly performed. The control circuit unit regards the selected memory cell as excessive retry operation and inhibits the selected memory cell in accordance with the number of times of the excessive retry operation when the number of times of the retry operation is over k times.

Abstract: A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of cell array blocks and a control circuit. The control circuit sets a selected bit line to have 0 volt, applies a first electric potential which is higher than 0 volt to a selected word line, applies a second electric potential which is higher than 0 volt and lower than the first electric potential to non-selected word lines other than the selected word line, applies a third electric potential which is 0 volt or more and lower than the second electric potential to a non-selected bit line adjacent to the selected bit line in an adjacent cell array block, applies the second electric potential to non-selected bit lines other than the non-selected bit line to which the third electric potential is applied, and changes a resistance status of the resistance variable film of the selected memory cell.

Abstract: A control circuit is configured to perform, when a plurality of variable resistance elements connected to a selected first wiring line are selected, a read operation to sense a voltage of the selected first wiring line. The control circuit is configured to adjust, according to the voltage of the selected first wiring line sensed in the read operation, a voltage to be applied to the selected first wiring line in a reset operation or a set operation. The reset operation is an operation to increase resistance of a variable resistance element. The set operation is an operation to decrease resistance of a variable resistance element.