Patents by Inventor Yoichi Momose

Yoichi Momose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10755641
    Abstract: An electro-optical device includes scan line, data line, pixel circuit located at a position corresponding to an intersection of the scan line and the data line, a first high potential line supplies a first potential, a low potential line supplies a second potential, and a second high potential line supplies a third potential. The pixel circuit includes a light emitting element, a memory circuit disposed between the first high potential line and the low potential line, a first transistor including a gate electrically connected to the memory circuit, and a second transistor including a gate electrically connected to the scan line. The second transistor is disposed between the memory circuit and f the data line. A potential difference between the first potential and the second potential is smaller than a potential difference between the third potential and the second potential.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 25, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi Miyasaka, Yoichi Momose
  • Patent number: 10754204
    Abstract: A method of manufacturing a liquid crystal device having a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween, and a sealing member formed in a peripheral portion of at least one of the substrates. The method includes forming the sealing member, disposing the liquid crystal layer inside the sealing member, and bonding the first substrate to the second substrate. In forming the sealing member, a ring-shaped portion that seals the liquid crystal layer inside the sealing member, a first sealing layer and a second sealing layer that face each other to be separated from each other are formed. In the bonding of the first substrate to the second substrate, a junction portion is formed in which the first and second sealing layers are pressed and joined outside the sealing member so as to form the ring-shaped portion.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 25, 2020
    Assignee: 138 East LCD Advancements Limited
    Inventors: Yoichi Momose, Satoshi Hasegawa
  • Patent number: 10748487
    Abstract: An electro-optical device includes a scan line, a data line, a pixel circuit provided at an intersection of the scan line and the data line, a first high potential line, a first low potential line, a second high potential line, and a second low potential line. The pixel circuit includes a light emitting device, a memory circuit disposed between the first high potential line and the first low potential line, a first transistor of N-type including a gate electrically connected to the memory circuit, and a second transistor disposed between the memory circuit and the data line. The light emitting device and the first transistor are disposed in series between the second high potential line and the second low potential line.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 18, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi Miyasaka, Yoichi Momose
  • Publication number: 20200241339
    Abstract: An electro-optical device may include a first substrate, a second substrate, a seal member extending in a first direction and disposed between the first and second substrates in a seal region defined around a pixel area, a first conductive layer disposed between the first substrate and the seal member and extending in a second direction intersecting with the first direction, a second conductive layer disposed between the first substrate and the first conductive layer and extending in the second direction, a third layer disposed in the pixel area and formed of the first conductive layer, and a fourth layer disposed in the pixel area and formed of the second conductive layer. In plan view, the first conductive layer overlaps the second conductive layer in the seal region. In a cross-sectional view the first direction, the second conductive layer is larger in an outer shape than the first conductive layer.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Yusuke Kinoe, Yoichi Momose
  • Patent number: 10685599
    Abstract: An electro-optical device includes a pixel circuit provided to correspond to an intersection of a scan line and a data line, a low potential line, and a high potential line. The pixel circuit includes a light emitting element, a first transistor, and a memory circuit including a first inverter, a second inverter, and a second transistor. The first transistor is disposed between an first input terminal of the first inverter and the data line. The second transistor is disposed between an second output terminal of the second inverter and the first input terminal. An first output terminal of the first inverter is electrically connected to an second input terminal of the second inverter. When the first transistor is in an ON-state, the second transistor is in an OFF-state.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 16, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi Miyasaka, Yoichi Momose, Kiyoshi Sekijima
  • Patent number: 10649280
    Abstract: An electro-optical device may include a first substrate including a pixel area in which a plurality of pixels are aligned, a second substrate, a seal member disposed between the first substrate and the second substrate so as to bond the first substrate and the second substrate together, the seal member being disposed in a seal region defined around the pixel area, a first conductive layer disposed between the first substrate and the seal member, a second conductive layer disposed between the first conductive layer and the first substrate, a third layer disposed in the pixel area and formed of the first conductive layer, and a fourth layer disposed in the pixel area and formed of the second conductive layer. The second conductive layer is larger in an outer shape than the first conductive layer in the seal region in plan view.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: May 12, 2020
    Assignee: Seiko Epson Corporation
    Inventors: Yusuke Kinoe, Yoichi Momose
  • Patent number: 10636353
    Abstract: An electro-optical device a pixel circuit located at a position corresponding to an intersection of a scan line and a data line, a first potential line supplies a first potential, a second potential line supplies a second potential, and a third potential line supplies a third potential. The pixel circuit includes a light emitting element and a memory circuit. The memory circuit that is disposed between the first potential line and the second potential line, and that includes a first transistor. A source of the first transistor is electrically connected to the first potential line. The light emitting element is disposed between a drain of the first transistor and the third potential line. An absolute value of a potential between the first potential and the second potential is smaller than an absolute value of a potential between the third potential and the second potential.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 28, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi Miyasaka, Yoichi Momose, Kiyoshi Sekijima
  • Publication number: 20200111425
    Abstract: Provided are a scan line, a data line, a pixel circuit provided corresponding to an intersection between the scan line and the data line, and an enable line. The pixel circuit includes a memory circuit, a light-emitting element, and an enable line driving circuit, the light-emitting element changes luminance in accordance with an image signal retained in the memory circuit, the enable line driving circuit controls a light emission enabled state of the light-emitting element, the pixel circuit includes a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, the enable line includes a first enable line and a second enable line, the first pixel circuit and the second pixel circuit are electrically connected with the first enable line, and the third pixel circuit and the fourth pixel circuit are electrically connected with the second enable line.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 9, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA
  • Patent number: 10614760
    Abstract: An electro-optical device includes a first scan line, a data line, and a pixel circuit provided at a position corresponding to intersections of the first scan line and the data line. The pixel circuit includes a light emitting element, a memory circuit, a first transistor, and a second transistor. The first transistor is electrically connected in series to the light emitting element, and a gate of the first transistor is electrically connected to the memory circuit. The second transistor is disposed between the data line and an input of a first inverter. The third transistor is disposed between an output terminal of a second inverter and the input of the first inverter. When the second transistor turns from an OFF-state to an ON-state, the third transistor is not in an ON-state.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 7, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi Miyasaka, Yoichi Momose, Kiyoshi Sekijima
  • Patent number: 10607536
    Abstract: An electro-optical device includes a pixel circuit located at a position corresponding to an intersection of a scan line and a data line, a low potential line, and a high potential line. The pixel circuit includes a light emitting element, a first transistor, a memory circuit including a first inverter, a second inverter, and a second transistor, and a third transistor. The first transistor is disposed between an input of the first inverter and the data line. The second transistor is disposed between an output of the second inverter and the input. The third transistor and the light emitting element are disposed between the low potential line and the memory circuit. When the first transistor is in an ON-state, the second transistor and the third transistor are in an OFF-state.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 31, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi Miyasaka, Yoichi Momose, Kiyoshi Sekijima
  • Patent number: 10564483
    Abstract: A method of manufacturing a liquid crystal device having a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween, and a sealing member formed in a peripheral portion of at least one of the substrates. The method includes forming the sealing member, disposing the liquid crystal layer inside the sealing member, and bonding the first substrate to the second substrate. In forming the sealing member, a ring-shaped portion that seals the liquid crystal layer inside the sealing member, a first sealing layer and a second sealing layer that face each other to be separated from each other are formed. In the bonding of the first substrate to the second substrate, a junction portion is formed in which the first and second sealing layers are pressed and joined outside the sealing member so as to form the ring-shaped portion.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: February 18, 2020
    Assignee: 138 EAST LCD ADVANCEMENTS LIMITED
    Inventors: Yoichi Momose, Satoshi Hasegawa
  • Patent number: 10497312
    Abstract: An electro-optical device includes a scan line, a data line, a pixel circuit provided to correspond to an intersection of the scan line and the data line, a low potential line, and a high potential line with a different potential from the low potential line. The pixel circuit includes a light emitting element, a memory circuit including a first transistor, a second transistor arranged between the memory circuit and the data line, and a third transistor. A source of the first transistor is electrically connected to the low potential line, and the light emitting element and the third transistor are arranged in series between a drain of the first transistor and the high potential line.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 3, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi Miyasaka, Yoichi Momose
  • Patent number: 10429637
    Abstract: An electro-optical device includes a mirror being positioned above a surface of a substrate and modulating light, and a torsion hinge being positioned between the mirror and the substrate and pivotably supporting the mirror. The electro-optical device includes beam portions being disposed between the mirror and the substrate at positions that do not overlap the mirror in plan view, and being supported by the substrate while being spaced away from the mirror and the substrate. Spring tips that regulate a pivot range of the mirror protrude from the beam portions toward positions that overlap the mirror in plan view.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 1, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kikuya Morita, Takunori Iki, Yoichi Momose
  • Publication number: 20190259336
    Abstract: An electro-optical device includes a first scan line, a second scan line, a data line, a pixel circuit located at a position corresponding to an intersection of the data line and each of the first scan line and the second scan line, and a scan line drive circuit supplying one of a selection signal and a non-selection signal to the first scan line and supplying one of a maintain signal and a non-maintain signal to the second scan line. The scan line drive circuit is capable of output the selection signal and the non-maintain signal during an identical period.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 22, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA
  • Publication number: 20190259132
    Abstract: An electro-optical device includes a pixel circuit 41G, a pixel circuit 41B, a high potential line 47G configured to supply a high potential VDDG to the pixel circuit 41G, a high potential line 47B configured to supply a high potential VDDB to the pixel circuit 41B, and a low potential line 46 configured to supply a first low potential VSS1 to the pixel circuit 41G and the pixel circuit 41B. The pixel circuit 41G includes a light-emitting element 20G configured to display G, the pixel circuit 41B includes a light-emitting element 20B configured to display B, and the high potential VDDG and the high potential VDDB are mutually independent.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA
  • Publication number: 20190235250
    Abstract: An electro-optical device includes a scan line, a data line, a pixel circuit, and an enable line. The pixel circuit includes a memory circuit, a light emitting element, and a first transistor. The light emitting element changes brightness in response to an image signal held in the memory circuit. The first transistor controls light emission and non-light-emission of the light emitting element. A field for displaying a single image each includes a sub-field (SF1) and a sub-field (SF2). The sub-field (SF1) and the sub-field (SF2) include a non-display period during which the light emitting element does not emit light and a display period during which the light emitting element is allowed to emit light. A length of the display period in the sub-field (SF1) is different from a length of the display period in the sub-field (SF2).
    Type: Application
    Filed: January 29, 2019
    Publication date: August 1, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA
  • Publication number: 20190197947
    Abstract: An electro-optical device a pixel circuit located at a position corresponding to an intersection of a scan line and a data line, a first potential line supplies a first potential, a second potential line supplies a second potential, and a third potential line supplies a third potential. The pixel circuit includes a light emitting element and a memory circuit. The memory circuit that is disposed between the first potential line and the second potential line, and that includes a first transistor. A source of the first transistor is electrically connected to the first potential line. The light emitting element is disposed between a drain of the first transistor and the third potential line. An absolute value of a potential between the first potential and the second potential is smaller than an absolute value of a potential between the third potential and the second potential.
    Type: Application
    Filed: December 27, 2018
    Publication date: June 27, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA
  • Publication number: 20190197951
    Abstract: An electro-optical device includes a first scan line, a data line, and a pixel circuit provided at a position corresponding to intersections of the first scan line and the data line. The pixel circuit includes a light emitting element, a memory circuit, a first transistor, and a second transistor. The first transistor is electrically connected in series to the light emitting element, and a gate of the first transistor is electrically connected to the memory circuit. The second transistor is disposed between the data line and an input of a first inverter. The third transistor is disposed between an output terminal of a second inverter and the input of the first inverter. When the second transistor turns from an OFF-state to an ON-state, the third transistor is not in an ON-state.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA
  • Publication number: 20190189051
    Abstract: An electro-optical device includes a pixel circuit located at a position corresponding to an intersection of a scan line and a data line, a low potential line, and a high potential line. The pixel circuit includes a light emitting element, a first transistor, a memory circuit including a first inverter, a second inverter, and a second transistor, and a third transistor. The first transistor is disposed between an input of the first inverter and the data line. The second transistor is disposed between an output of the second inverter and the input. The third transistor and the light emitting element are disposed between the low potential line and the memory circuit. When the first transistor is in an ON-state, the second transistor and the third transistor are in an OFF-state.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 20, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA
  • Publication number: 20190164479
    Abstract: An electro-optical device includes a pixel circuit provided to correspond to an intersection of a scan line and a data line, a low potential line, and a high potential line. The pixel circuit includes a light emitting element, a first transistor, and a memory circuit including a first inverter, a second inverter, and a second transistor. The first transistor is disposed between an first input terminal of the first inverter and the data line. The second transistor is disposed between an second output terminal of the second inverter and the first input terminal. An first output terminal of the first inverter is electrically connected to an second input terminal of the second inverter. When the first transistor is in an ON-state, the second transistor is in an OFF-state.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsutoshi MIYASAKA, Yoichi MOMOSE, Kiyoshi SEKIJIMA