Patents by Inventor Yoichiro Tanaka

Yoichiro Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10372088
    Abstract: There is provided a power consumption management device including a power measurement unit configured to measure power consumption of an electrical device, an environmental factor measurement unit configured to measure a factor of an environment in which the electrical device is used, a storage unit configured to store a predicted value related to the power consumption in which a value of the factor of the environment is designated as a parameter, and a calculation/control unit. The calculation/control unit obtains the predicted value related to the power consumption stored in the storage unit based on the value of the factor of the environment measured by the environmental factor measurement unit and compares the obtained predicted value related to the power consumption to an actual measurement value related to the power consumption obtained based on a power consumption value measured by the power measurement unit.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 6, 2019
    Assignee: Sony Corporation
    Inventors: Yoichiro Sako, Takanori Washiro, Kazutoshi Serita, Taro Tadano, Kazuyoshi Takemura, Kuniya Hayashi, Kayoko Tanaka
  • Patent number: 10344777
    Abstract: In an ejector, formed in a body is a swirling space which lets a high-pressure refrigerant flowing from a refrigerant inlet port swirl and introduces the swirling high-pressure refrigerant into a depressurizing space in which the swirled high-pressure refrigerant is depressurized and expanded. A passage formation member that defines a nozzle passage and a diffuser passage is shaped to have a cross-sectional area increasing with distance from the depressurizing space. Further, a temperature sensing unit of a drive device that displaces the passage formation member is housed in the body, and the temperature sensing unit and a diaphragm have annular shapes to surround at least the axial line of the passage formation member.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: July 9, 2019
    Assignee: DENSO CORPORATION
    Inventors: Eitaro Tanaka, Toru Takahashi, Satoshi Inoue, Haruyuki Nishijima, Etsuhisa Yamada, Yoichiro Kawamoto
  • Publication number: 20190145021
    Abstract: An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.
    Type: Application
    Filed: May 9, 2017
    Publication date: May 16, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takanori TANAKA, Shigehisa YAMAMOTO, Yu NAKAMURA, Yasuhiro KIMURA, Shuhei NAKATA, Yoichiro MITANI
  • Patent number: 10290680
    Abstract: Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 14, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Yoichiro Tanaka
  • Patent number: 10026782
    Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 17, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
  • Publication number: 20170309681
    Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 26, 2017
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
  • Publication number: 20170236871
    Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.
    Type: Application
    Filed: March 30, 2016
    Publication date: August 17, 2017
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
  • Patent number: 9735202
    Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 15, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
  • Publication number: 20170125483
    Abstract: Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Applicant: SANDISK 3D LLC
    Inventor: Yoichiro Tanaka
  • Patent number: 9443910
    Abstract: A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the bit lines. The reversible resistivity material may be a metal oxide. The metal that is used to form the silicide may serve as an oxygen scavenger to draw oxygen away from the silicon, thus preventing formation of silicon oxide between the reversible resistivity material and the bit line. The metal silicide may also help prevent formation of a depletion layer in silicon in the bit line.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 13, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Kan Fujiwara, Takuya Futase, Toshihiro Iizuka, Shin Kikuchi, Yoichiro Tanaka, Akio Nishida, Christopher J Petti
  • Patent number: 8969923
    Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: March 3, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Publication number: 20140328105
    Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.
    Type: Application
    Filed: July 17, 2014
    Publication date: November 6, 2014
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 8816041
    Abstract: Provided are a polyester polymerization catalyst with which the generation of foreign materials caused by the catalyst or mold pollution at the time of molding are reduced and polyesters having remarkably superior thermal stability and color tone can be obtained. Provided is a polyester polymerization catalyst produced by the reaction of a titanium compound and a mannitol in a molar ratio of titanium atom to mannitol of from 1:1 to 1:3. A method for producing a polyester employs the polyester polymerization catalyst.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: August 26, 2014
    Assignee: Toray Industries, Inc.
    Inventors: Yoichiro Tanaka, Eri Hatano, Keisuke Honda
  • Patent number: 8809128
    Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: August 19, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 8741696
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: June 3, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 8679967
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: March 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Yoichiro Tanaka
  • Publication number: 20120322970
    Abstract: To provide a method of producing a biomass resource-derived polyester capable of greatly reducing fossil resource usage amounts and carbon dioxide increases that is in way inferior in color or thermal stability to a conventional fossil resource-derived product while also having superior dye affinity. The biomass resource-derived dicarboxylic acid and/or ester forming derivative thereof used as the raw material fulfills at least one of the following conditions: (A) The amount of potassium hydroxide needed to neutralize an acid component extracted using an organic solvent from 1 g of the dicarboxylic acid and/or ester forming derivative thereof is 0.1 mg KOH/g or less (B) The amount of potassium hydroxide needed to neutralize an acid component extracted using water from 1 g of the dicarboxylic acid and/or ester forming derivative thereof is 0.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 20, 2012
    Inventors: Matthew W. Peters, Kunihiro Morimoto, Yoichiro Tanaka, Takuro Okubo, Yoshiaki Murata
  • Patent number: 8224160
    Abstract: A disk replay device includes a non-volatile storage unit, which forms a file list from file information including the file name of a compressed video file and the like, and from the number of times that viewing of the file is possible, and stores this file list. At the stage that a disk is set into a disk setting unit, this file list is created based upon information which has been acquired from a compressed video file recorded upon the disk. Moreover, the disk replay device includes a display unit which displays the file list stored in the storage unit, when a predetermined operation is performed by the operator, so that the operator is able to recognize, for each file, the number of times that viewing is possible.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: July 17, 2012
    Assignee: Funai Electric Co., Ltd.
    Inventor: Yoichiro Tanaka
  • Patent number: 8193074
    Abstract: A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: June 5, 2012
    Assignee: SanDisk 3D LLC
    Inventor: Yoichiro Tanaka
  • Patent number: 8124971
    Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 28, 2012
    Assignee: SanDisk 3D LLC
    Inventor: Yoichiro Tanaka