Patents by Inventor Yoichiro Tanaka
Yoichiro Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210054188Abstract: A highly hygroscopic sea-island type composite fiber has characteristics (1)-(4) below: (1) the island component in a polymer has hygroscopicity; (2) the ratio of the outermost layer thickness T to the fiber diameter R in a cross section of the fiber is 0.05-0.25; (3) the difference (?MR) in moisture absorption rate after hot water treatment is 2.0-10.0%; and (4) the content of a phenol group is 16-160 mmol/kg, wherein the outermost layer thickness is the difference between the radius of the fiber and the radius of a circumscribed circle connecting the vertices of the island component disposed at the outermost circumference, and represents the thickness of the sea component present in the outermost layer.Type: ApplicationFiled: March 8, 2019Publication date: February 25, 2021Applicant: Toray Industries, Inc.Inventors: Masataka MAKINO, Junichi NAKAGAWA, Yoichiro TANAKA, Katsuhiko MOCHIZUKI
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Patent number: 10290680Abstract: Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.Type: GrantFiled: October 30, 2015Date of Patent: May 14, 2019Assignee: SANDISK TECHNOLOGIES LLCInventor: Yoichiro Tanaka
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Patent number: 10026782Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: GrantFiled: June 26, 2017Date of Patent: July 17, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Publication number: 20170309681Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: ApplicationFiled: June 26, 2017Publication date: October 26, 2017Applicant: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Publication number: 20170236871Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: ApplicationFiled: March 30, 2016Publication date: August 17, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Patent number: 9735202Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.Type: GrantFiled: March 30, 2016Date of Patent: August 15, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yoichiro Tanaka, Yangyin Chen, Chu-Chen Fu, Christopher Petti
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Publication number: 20170125483Abstract: Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line (e.g., TiN) may be arranged adjacent to a ReRAM material (e.g., HfOx) that is adjacent to a first metal (e.g., TiN) that is adjacent to the intrinsic polysilicon region. The first metal may comprise a metal, metal-nitride, or a metal-silicide. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal (e.g., TiN) that is adjacent to a second metal different from the first metal (e.g., tungsten) that is adjacent to the intrinsic polysilicon region.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: SANDISK 3D LLCInventor: Yoichiro Tanaka
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Patent number: 9443910Abstract: A three-dimensional (3D) non-volatile memory array having a silicide bit line and method of fabricating is disclosed. The fabrication technique may comprise forming a metal silicide for at least a portion of the bit line. The device has reversible resistivity material between the word lines and the bit lines. The reversible resistivity material may be a metal oxide. The metal that is used to form the silicide may serve as an oxygen scavenger to draw oxygen away from the silicon, thus preventing formation of silicon oxide between the reversible resistivity material and the bit line. The metal silicide may also help prevent formation of a depletion layer in silicon in the bit line.Type: GrantFiled: July 9, 2015Date of Patent: September 13, 2016Assignee: SanDisk Technologies LLCInventors: Kan Fujiwara, Takuya Futase, Toshihiro Iizuka, Shin Kikuchi, Yoichiro Tanaka, Akio Nishida, Christopher J Petti
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Patent number: 8969923Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.Type: GrantFiled: July 17, 2014Date of Patent: March 3, 2015Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
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Publication number: 20140328105Abstract: Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.Type: ApplicationFiled: July 17, 2014Publication date: November 6, 2014Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
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Patent number: 8816041Abstract: Provided are a polyester polymerization catalyst with which the generation of foreign materials caused by the catalyst or mold pollution at the time of molding are reduced and polyesters having remarkably superior thermal stability and color tone can be obtained. Provided is a polyester polymerization catalyst produced by the reaction of a titanium compound and a mannitol in a molar ratio of titanium atom to mannitol of from 1:1 to 1:3. A method for producing a polyester employs the polyester polymerization catalyst.Type: GrantFiled: August 18, 2009Date of Patent: August 26, 2014Assignee: Toray Industries, Inc.Inventors: Yoichiro Tanaka, Eri Hatano, Keisuke Honda
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Patent number: 8809128Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.Type: GrantFiled: October 26, 2010Date of Patent: August 19, 2014Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
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Patent number: 8741696Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.Type: GrantFiled: October 26, 2010Date of Patent: June 3, 2014Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
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Patent number: 8679967Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.Type: GrantFiled: October 26, 2010Date of Patent: March 25, 2014Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Yoichiro Tanaka
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Publication number: 20120322970Abstract: To provide a method of producing a biomass resource-derived polyester capable of greatly reducing fossil resource usage amounts and carbon dioxide increases that is in way inferior in color or thermal stability to a conventional fossil resource-derived product while also having superior dye affinity. The biomass resource-derived dicarboxylic acid and/or ester forming derivative thereof used as the raw material fulfills at least one of the following conditions: (A) The amount of potassium hydroxide needed to neutralize an acid component extracted using an organic solvent from 1 g of the dicarboxylic acid and/or ester forming derivative thereof is 0.1 mg KOH/g or less (B) The amount of potassium hydroxide needed to neutralize an acid component extracted using water from 1 g of the dicarboxylic acid and/or ester forming derivative thereof is 0.Type: ApplicationFiled: June 15, 2012Publication date: December 20, 2012Inventors: Matthew W. Peters, Kunihiro Morimoto, Yoichiro Tanaka, Takuro Okubo, Yoshiaki Murata
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Patent number: 8224160Abstract: A disk replay device includes a non-volatile storage unit, which forms a file list from file information including the file name of a compressed video file and the like, and from the number of times that viewing of the file is possible, and stores this file list. At the stage that a disk is set into a disk setting unit, this file list is created based upon information which has been acquired from a compressed video file recorded upon the disk. Moreover, the disk replay device includes a display unit which displays the file list stored in the storage unit, when a predetermined operation is performed by the operator, so that the operator is able to recognize, for each file, the number of times that viewing is possible.Type: GrantFiled: October 11, 2006Date of Patent: July 17, 2012Assignee: Funai Electric Co., Ltd.Inventor: Yoichiro Tanaka
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Patent number: 8193074Abstract: A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.Type: GrantFiled: November 21, 2008Date of Patent: June 5, 2012Assignee: SanDisk 3D LLCInventor: Yoichiro Tanaka
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Patent number: 8124971Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.Type: GrantFiled: March 30, 2007Date of Patent: February 28, 2012Assignee: SanDisk 3D LLCInventor: Yoichiro Tanaka
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Patent number: 8071475Abstract: A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.Type: GrantFiled: September 28, 2007Date of Patent: December 6, 2011Assignee: SanDisk 3D LLCInventors: Yoichiro Tanaka, Steven J. Radigan, Usha Raghuram
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Publication number: 20110178265Abstract: Provided are a polyester polymerization catalyst with which the generation of foreign materials caused by the catalyst or mold pollution at the time of molding are reduced and polyesters having remarkably superior thermal stability and color tone can be obtained. Provided is a polyester polymerization catalyst produced by the reaction of a titanium compound and a mannitol in a molar ratio of titanium atom to mannitol of from 1:1 to 1:3. A method for producing a polyester employs the polyester polymerization catalyst.Type: ApplicationFiled: August 18, 2009Publication date: July 21, 2011Applicant: Toray Industries, Inc.Inventors: Yoichiro Tanaka, Eri Hatano, Keisuke Honda