Patents by Inventor Yoichiro Tanaka

Yoichiro Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8193074
    Abstract: A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: June 5, 2012
    Assignee: SanDisk 3D LLC
    Inventor: Yoichiro Tanaka
  • Patent number: 8124971
    Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 28, 2012
    Assignee: SanDisk 3D LLC
    Inventor: Yoichiro Tanaka
  • Patent number: 8071475
    Abstract: A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: December 6, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Yoichiro Tanaka, Steven J. Radigan, Usha Raghuram
  • Publication number: 20110178265
    Abstract: Provided are a polyester polymerization catalyst with which the generation of foreign materials caused by the catalyst or mold pollution at the time of molding are reduced and polyesters having remarkably superior thermal stability and color tone can be obtained. Provided is a polyester polymerization catalyst produced by the reaction of a titanium compound and a mannitol in a molar ratio of titanium atom to mannitol of from 1:1 to 1:3. A method for producing a polyester employs the polyester polymerization catalyst.
    Type: Application
    Filed: August 18, 2009
    Publication date: July 21, 2011
    Applicant: Toray Industries, Inc.
    Inventors: Yoichiro Tanaka, Eri Hatano, Keisuke Honda
  • Publication number: 20110095438
    Abstract: The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 28, 2011
    Applicant: SANDISK 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Publication number: 20110095434
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 28, 2011
    Applicant: SANDISK 3D LLC
    Inventors: Roy E. Scheuerlein, Yoichiro Tanaka
  • Publication number: 20110095338
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory structures methods of forming pillars for memory cells using sequential sidewall patterning. The invention includes forming first features from a first template layer disposed above a memory layer stack; forming first sidewall spacers adjacent the first features; forming second features that extend in a first direction in a mask layer by using the first sidewall spacers as a hardmask; depositing a second template layer on the mask layer; forming third features from the second template layer; forming second sidewall spacers adjacent the third features; and forming fourth features that extend in a second direction in the mask layer by using the second sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 28, 2011
    Applicant: SANDISK 3D LLC
    Inventors: Roy E. Scheuerlein, Christopher J. Petti, Yoichiro Tanaka
  • Patent number: 7927977
    Abstract: A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: April 19, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Raghuveer S. Makala, Vance Dunton, Yoichiro Tanaka, Steven Maxwell, Tong Zhang, Steven J. Radigan
  • Publication number: 20110014779
    Abstract: A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 20, 2011
    Inventors: Raghuveer S. Makala, Vance Dunton, Yoichiro Tanaka, Steven Maxwell, Tong Zhang, Steven J. Radigan
  • Patent number: 7831128
    Abstract: A video and audio recording apparatus including: a plurality of tuner units each of which receives commercial broadcasting to output video and audio signals; a distributor that distributes high-frequency signals input to an input terminal from the outside of an apparatus body to the plurality of tuner units; a video and audio recording unit that simultaneously records the video and audio signals output from the plurality of tuner units; and a remote controller that is provided with tuner switching keys for switching, in a predetermined order, a tuner unit which sets receiving channels or records the video and audio signals to be output, among the plurality of tuner units, whenever the switching key is operated.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: November 9, 2010
    Assignee: Funai Electric Co., Ltd.
    Inventor: Yoichiro Tanaka
  • Publication number: 20100127358
    Abstract: A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Inventor: Yoichiro Tanaka
  • Patent number: 7629253
    Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: December 8, 2009
    Assignee: Sandisk 3D LLC
    Inventor: Yoichiro Tanaka
  • Publication number: 20090166610
    Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) fabricating a carbon nano-tube (CNT) material above the first conductor; (3) depositing a dielectric material onto a top surface of the CNT material; (4) planarizing the dielectric material to expose at least a portion of the CNT material; (5) fabricating a diode above the first conductor; and (6) fabricating a second conductor above the CNT material and the diode. Numerous other aspects are provided.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: April Schricker, Mark Clark, Brad Herner, Yoichiro Tanaka
  • Publication number: 20090085087
    Abstract: A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: SanDisk Corporation
    Inventors: Yoichiro Tanaka, Steven J. Radigan, Usha Raghuram
  • Patent number: 7443626
    Abstract: A patterned disk medium includes a disk-shaped flat substrate including a first surface and a second surface located an opposite side of the first surface. First servo pattern areas including portions provided with magnetic members and portions provided with no magnetic members are provided on the first surface. Second servo pattern areas including portions provided with magnetic members and portions provided with no magnetic members are provided on the second surface. The magnetic members of the first and second servo pattern areas are magnetized in a direction perpendicular to the first and second surfaces. The magnetic polarity of the surfaces of the magnetic members of the second pattern areas differs from that of the surfaces of the magnetic members of the first pattern areas.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: October 28, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Asakura, Yoichiro Tanaka, Akira Kikitsu
  • Publication number: 20080237862
    Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventor: Yoichiro Tanaka
  • Publication number: 20080242080
    Abstract: One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventor: Yoichiro Tanaka
  • Patent number: 7319568
    Abstract: A magnetic recording media has a magnetic layer formed on a substrate and includes data regions including a magnetic pattern constituting a recoding track and servo regions including magnetic patterns used as address bits, the data regions and the servo regions being contained in a plane of the magnetic layer. In a case where two magnetic patterns used as address bits on the servo regions corresponding to two adjacent recording tracks are arranged in such a manner that one corner of one of the magnetic patterns is closest to one corner of the other, the corners of the two magnetic patterns are substantially joined together.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: January 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Okino, Akira Kikitsu, Yoichiro Tanaka, Yoshiyuki Kamata
  • Patent number: 7277262
    Abstract: A magnetic recording/reproducing apparatus has a magnetoresistive head having a magnetoresistive film through which a current is flowed in a direction substantially perpendicular to a film plane and a pair of magnetic shields disposed to sandwich the magnetoresistive film, and a preamplifier which supplies a sense current to the magnetoresistive head in constant-current driving.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: October 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Takagishi, Tomomi Funayama, Yoichiro Tanaka
  • Publication number: 20070081797
    Abstract: A disk replay device includes a non-volatile storage unit, which forms a file list from file information including the file name of a compressed video file and the like, and from the number of times that viewing of the file is possible, and stores this file list. At the stage that a disk is set into a disk setting unit, this file list is created based upon information which has been acquired from a compressed video file recorded upon the disk. Moreover, the disk replay device includes a display unit which displays the file list stored in the storage unit, when a predetermined operation is performed by the operator, so that the operator is able to recognize, for each file, the number of times that viewing is possible.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 12, 2007
    Applicant: FUNAI ELECTRIC CO., LTD.
    Inventor: Yoichiro Tanaka