Abstract: A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal; a divisional program control circuit configured to generate a divisional programming enable signal according to a predetermined number of program division times, in response to the program completion signal; and a controller configured to generate the programming enable signal in response to the divisional programming enable signal.

Abstract: A semiconductor memory apparatus includes a program pulse generation block configured to generate a first write control signal, second write control signal and a program completion signal in response to a programming enable signal; a set program control circuit configured to repeatedly generate a set programming enable signal a predetermined number of times in response to an erase command and the program completion signal; and a controller configured to disable the first write control signal in response to the erase command and generate the programming enable signal in response to the set programming enable signal.

Abstract: A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal in response to a programming enable signal; a successive program control circuit configured to generate a successive programming enable signal in response to received program addresses and data count signals as a buffered program command or a buffered overwrite command; and a controller configured to generate the programming enable signal in response to the successive programming enable signal.

Abstract: A semiconductor memory apparatus includes a period control signal generation unit configured to generate a period control signal which is activated after a first time, in response to a programming enable signal, a first write control code generation unit configured to generate first write control codes which are cyclically updated for a second time, in response to the programming enable signal, and update the first write control codes in response to the period control signal, a second write control code generation unit configured to generate a second write control code in response to the programming enable signal, and a data write unit configured to output a first programming current pulse which has a magnitude corresponding to a code combination of the updated first write control codes or a second programming current pulse which has a magnitude corresponding to the second write control code.

Abstract: A semiconductor apparatus includes a first write control code generation unit configured to generate first write control codes which have fixed value for a first time and are cyclically updated after the first time, a second write control code generation unit configured to generate a second write control code, and a data write unit configured to output a first programming current pulse in response to the first write control codes, or a second programming current pulse in response to the second write control code.

Abstract: A semiconductor memory apparatus includes a first write control code generation unit configured to generate a first write control code which is updated with different cycles which have different periods, in response to a programming verification flag signal and a programming enable signal, and a data write unit configured to output a first programming current pulse with a magnitude corresponding to a code combination of the first write control code which is updated.

Abstract: A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a magnitude corresponding to the code value of the write control code.

Abstract: A semiconductor memory apparatus includes a program pulse generation block configured to generate a first write control signal, second write control signal and a program completion signal in response to a programming enable signal; a set program control circuit configured to repeatedly generate a set programming enable signal a predetermined number of times in response to an erase command and the program completion signal; and a controller configured to disable the first write control signal in response to the erase command and generate the programming enable signal in response to the set programming enable signal.

Abstract: A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal in response to a programming enable signal; a successive program control circuit configured to generate a successive programming enable signal in response to received program addresses and data count signals as a buffered program command or a buffered overwrite command; and a controller configured to generate the programming enable signal in response to the successive programming enable signal.

Abstract: A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal; a divisional program control circuit configured to generate a divisional programming enable signal according to a predetermined number of program division times, in response to the program completion signal; and a controller configured to generate the programming enable signal in response to the divisional programming enable signal.

Abstract: A semiconductor memory apparatus includes: a first write control code generation unit configured to generate first write control codes which are updated with different cycles in a plurality of respective periods, in response to a programming verification flag signal and a programming enable signal, the first write control code generation unit determining the number of the plurality of periods depending upon a code value of the repetition times setting codes and an update cycle of the first write control codes in an initial period among the plurality of periods depending upon a code value of initial setting codes; and a data write unit configured to output a first programming current pulse with a magnitude corresponding to a code combination of the first write control codes which are updated.

Abstract: A semiconductor memory apparatus includes: a first write control code generation unit configured to generate first write control codes which are updated with different cycles in a plurality of respective periods, in response to a programming verification flag signal and a programming enable signal, the first write control code generation unit determining the number of the plurality of periods depending upon a code value of the repetition times setting codes and an update cycle of the first write control codes in an initial period among the plurality of periods depending upon a code value of initial setting codes; and a data write unit configured to output a first programming current pulse with a magnitude corresponding to a code combination of the first write control codes which are updated.

Abstract: A semiconductor memory apparatus includes a first write control code generation unit configured to generate a first write control code which is updated with different cycles which have different periods, in response to a programming verification flag signal and a programming enable signal, and a data write unit configured to output a first programming current pulse with a magnitude corresponding to a code combination of the first write control code which is updated.

Abstract: A semiconductor apparatus includes a memory array configured to store write data transmitted through data transmission lines and transmit stored data to the data transmission line as read data; a data write unit configured to drive the write data to the data transmission lines in response to a data write command; and a data read unit configured to sense the read data transmitted through the data transmission lines in response to a data read command when a data verification signal is deactivated and sense the write data transmitted through the data transmission lines in response to the data write command when the data verification signal is activated.

Abstract: A semiconductor memory apparatus includes a write control code generation unit configured to generate a write control code which is updated at each pulsing timing of an external test pulse signal applied through a pad; and a data write unit configured to output a programming current pulse which has a magnitude corresponding to the code value of the write control code.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.

Abstract: A semiconductor memory apparatus includes a period control signal generation unit configured to generate a period control signal which is activated after a first time, in response to a programming enable signal, a first write control code generation unit configured to generate first write control codes which are cyclically updated for a second time, in response to the programming enable signal, and update the first write control codes in response to the period control signal, a second write control code generation unit configured to generate a second write control code in response to the programming enable signal, and a data write unit configured to output a first programming current pulse which has a magnitude corresponding to a code combination of the updated first write control codes or a second programming current pulse which has a magnitude corresponding to the second write control code.

Abstract: A semiconductor apparatus includes a first write control code generation unit configured to generate first write control codes which have fixed value for a first time and are cyclically updated after the first time, a second write control code generation unit configured to generate a second write control code, and a data write unit configured to output a first programming current pulse in response to the first write control codes, or a second programming current pulse in response to the second write control code.

Abstract: A command processing circuit for generating internal command signals corresponding to a plurality of unit internal command signals sequentially applied during a plurality of command cycles, the command processing circuit includes a first command latching unit configured to latch a first unit internal command signal applied in a first command cycle and a second command latching unit configured to latch a second unit internal command signal in response to the first unit internal command signal latched in the first command latching unit in a second command cycle after the first command cycle, and output an internal command signal corresponding to the first unit internal command signal and the second unit internal command signal.

Abstract: A command processing circuit for generating internal command signals corresponding to a plurality of unit internal command signals sequentially applied during a plurality of command cycles, the command processing circuit includes a first command latching unit configured to latch a first unit internal command signal applied in a first command cycle and a second command latching unit configured to latch a second unit internal command signal in response to the first unit internal command signal latched in the first command latching unit in a second command cycle after the first command cycle, and output an internal command signal corresponding to the first unit internal command signal and the second unit internal command signal.