Abstract: A semiconductor memory device having a mode register set (MRS) includes: a decoding unit for decoding a plurality of address signals included in the MRS and outputting a plurality of decoded signals; and an output unit for outputting a plurality of configuration signals and activating one of the plurality of configuration signals in response to the plurality of decoded signals, wherein the output unit keeps its previous output signals if more than one of the plurality of decoded signals are activated.

Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: A semiconductor memory device having a mode register set (MRS) includes: a decoding unit for decoding a plurality of address signals included in the MRS and outputting a plurality of decoded signals; and an output unit for outputting a plurality of configuration signals and activating one of the plurality of configuration signals in response to the plurality of decoded signals, wherein the output unit keeps its previous output signals if more than one of the plurality of decoded signals are activated.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.

Abstract: An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and-testing a write operation of the semiconductor memory device.

Abstract: A decoding circuit of an on die termination (ODT) control signal for stably performing an ODT operation. The decoding circuit includes: a latch unit for receiving a plurality of input signals and for holding previous output signals of the latch unit when the plurality of input signals are in predetermined logic levels; and a decoding unit for decoding output signals of the latch unit in order to control ODT operation.