Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: A semiconductor memory device can reduce needless current consumption when addresses are inputted. A semiconductor memory device includes a clock enable buffering unit for receiving a clock enable signal to output a buffer enable signal, an address buffer control unit for generating an address buffer control signal in response to a plurality of data output mode, and an address buffering unit for receiving an address in response to the buffer enable signal and the address buffer control signal.

Abstract: A semiconductor memory device analyzes tRCD inferiority by simultaneously interlock-controlling an enable time of column address and an access time of cell data. The semiconductor memory device includes a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address, and an enable controller for outputting a plurality of control signals with different states in response to a test mode signal, outputting the bank control signal of which enable delay time is controlled by a selective activation state of the plurality of control signals in a read/write operation mode, and controlling a column address enable signal to activate the bank column address to have the same enable delay time as the bank control signal.

Abstract: An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the semiconductor memory device.

Abstract: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, corresponding to the N normal wordline and the M preliminary wordline; a refresh counting control block for resetting the refresh address counting block when the refresh address counts a predetermined count during a test mode; and a row decoding block for refreshing unit cells coupled to the N normal wordline and unit cells coupled to the M preliminary wordline of the memory cell block according to the refresh address and a redundancy control signal outputted from the refresh counting control block, wherein M, N are positive integers.

Abstract: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

Abstract: An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the semiconductor memory device.

Abstract: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by using an inputted address signal, and an internal power voltage level controller for controlling the levels of the internal power voltages by using the trimming selection signal that is outputted under control of the trimming enable signal.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.

Abstract: An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the semiconductor memory device.

Abstract: A decoding circuit of an on die termination (ODT) control signal for stably performing an ODT operation. The decoding circuit includes: a latch unit for receiving a plurality of input signals and for holding previous output signals of the latch unit when the plurality of input signals are in predetermined logic levels; and a decoding unit for decoding output signals of the latch unit in order to control ODT operation.

Abstract: A semiconductor memory device for broadening a data I/O window includes: a buffer driving block for generating a buffer driving signal in response to an additive delay signal and a CAS delay signal, wherein an activation period of the buffer driving signal is determined based on the additive delay signal and a combination of delayed additive delay signals; and a data buffer for receiving an external data at an activation of the buffer driving signal.

Abstract: A semiconductor memory device analyzes tRCD inferiority by simultaneously interlock-controlling an enable time of column address and an access time of cell data. The semiconductor memory device includes a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address, and an enable controller for outputting a plurality of control signals with different states in response to a test mode signal, outputting the bank control signal of which enable delay time is controlled by a selective activation state of the plurality of control signals in a read/write operation mode, and controlling a column address enable signal to activate the bank column address to have the same enable delay time as the bank control signal.

Abstract: An internal address generator includes a plurality of column address generators, a mode column address generator, and a drive clock generator. Each column generator receives a corresponding address, an additive latency, and a CAS latency to generate an internal read address in response to a read drive clock and generate an internal write address in response to a write drive clock. The mode column address generator receives a corresponding address, the additive latency, and the CAS latency to generate a mode read address in response to a band width read drive clock and generate a mode write address in response to a band width write drive clock. The drive clock generator receives an additive latency signal, a band width signal, a write enable signal, and a clock to generate the read drive clock, the write drive clock, the band width read drive clock, and the band width write drive clock.

Abstract: A semiconductor memory device can reduce needless current consumption when addresses are inputted. A semiconductor memory device includes a clock enable buffering unit for receiving a clock enable signal to output a buffer enable signal, an address buffer control unit for generating an address buffer control signal in response to a plurality of data output mode, and an address buffering unit for receiving an address in response to the buffer enable signal and the address buffer control signal.

Abstract: Provided is a decoding circuit for a memory device which is improved in an operation of chip so as to enable the operation to be predictable by making a decoded result corresponding to an undefined code get a specific value. The decoding circuit for a memory device generates address signals by control signals set with a mode, and comprises a first logical circuit for decoding and outputting a result value defined by logically-combining the address signals corresponding to a first group and a second logical circuit for performing a decoding operation to have address signals with a specific value included in the defined result value by logically-combining address signals corresponding to a second group, by dividing the address signals into the first group corresponding to at least one defined result value and the second group corresponding to an undefined result value.

Abstract: A semiconductor memory device for broadening a data I/O window includes: a buffer driving block for generating a buffer driving signal in response to an additive delay signal and a CAS delay signal, wherein an activation period of the buffer driving signal is determined based on the additive delay signal and a combination of delayed additive delay signals; and a data buffer for receiving an external data at an activation of the buffer driving signal.

Abstract: Disclosed herein is a semiconductor memory device for consuming a uniform amount of current. The semiconductor memory device includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, corresponding to the N normal wordline and the M preliminary wordline; a refresh counting control block for resetting the refresh address counting block when the refresh address counts a predetermined count during a test mode; and a row decoding block for refreshing unit cells coupled to the N normal wordline and unit cells coupled to the M preliminary wordline of the memory cell block according to the refresh address and a redundancy control signal outputted from the refresh counting control block, wherein M, N are positive integers.