Abstract: An electronic device which drives applications is provided. The electronic device includes a display partitioned into a first area and a second area, a memory configured to store the applications classified into a first group and a second group, and a processor configured to output a screen, associated with an execution of the first group, through the first area and output a screen, associated with an execution of the second group, through the second area.

Abstract: Provided are a carbon nanotube composite containing a carbon nanotube coated with a protein having a catechol group and a metal ion bound to the catechol group and a method for manufacturing the same. According to the present disclosure, a carbon nanotube composite which exhibits controllable dispersibility and degree of crosslinkage while retaining the intrinsic physical properties of the carbon nanotube may be prepared. Since the phase change and tendency of aggregation of the carbon nanotube composite can be controlled quickly and repeatedly depending on the change in external environment, the carbon nanotube composite may be useful in various industrial fields including medicine, environment, etc. as a self-healing material.

Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

Abstract: Embodiments of a superhydrophobic structure comprise a substrate and a hierarchical surface structure disposed on at least one surface of the substrate, wherein the hierarchical surface structure comprises a microstructure comprising a plurality of microasperities disposed in a spaced geometric pattern on at least one surface of the substrate. The fraction of the surface area of the substrate covered by the microasperities is from between about 0.1 to about 1. The hierarchical structure comprises a nanostructure comprising a plurality of nanoasperities disposed on at least one surface of the microstructure.

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.