Abstract: A liquid crystal display device includes a liquid crystal panel, a gate driver, a data driver, and an initial driving control unit. The liquid crystal panel includes a plurality of liquid crystal cells. Each liquid crystal cell is defined by a gate line, a data line and a thin film transistor. The gate driver controls the thin film transistor connected to the gate line of each liquid crystal cell according to a gate control signal. The data driver outputs a pixel signal to the data line of the each liquid crystal cell according to a data control signal. The data driver includes a switch connected to the data line of the each liquid crystal cell. The initial driving control unit is structured to compare a clock count with a predetermined reference value and operable to alternately generate a first state signal and a second state signal based on the comparison. The unit applies the first state signal to the switch during a masking interval.

Abstract: A driving circuit for a display apparatus is disclosed. The driving circuit includes a frame rate determiner for determining a frame rate based on a reference timing signal provided from a system. The driving circuit also includes a gamma reference voltage generator for generating a plurality of gamma reference voltages. The driving circuit further includes a gamma voltage generator for receiving the plurality of gamma reference voltages from the gamma reference voltage generator to generate a plurality of gamma voltage groups, for selecting gamma voltages included in any one of the plurality of gamma voltage groups based on a determination result from the frame rate determiner, and for outputting the selected gamma voltages.

Abstract: A liquid crystal display device includes a liquid crystal panel, a gate driver, a data driver, and an initial driving control unit. The liquid crystal panel includes a plurality of liquid crystal cells. Each liquid crystal cell is defined by a gate line, a data line and a thin film transistor. The gate driver controls the thin film transistor connected to the gate line of each liquid crystal cell according to a gate control signal. The data driver outputs a pixel signal to the data line of the each liquid crystal cell according to a data control signal. The data driver includes a switch connected to the data line of the each liquid crystal cell. The initial driving control unit is structured to compare a clock count with a predetermined reference value and operable to alternately generate a first state signal and a second state signal based on the comparison. The unit applies the first state signal to the switch during a masking interval.

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract: Disclosed is a composite of filler and polymer resin and a method for preparing the same, including preparing a thermoplastic resin composition by mixing a polymerization catalyst with a polymerizable thermoplastic resin, preparing a pre-pellet including a filler and a polymer resin by mixing a filler with the thermoplastic resin composition and heating to perform in-situ polymerization of the polymerizable thermoplastic resin to the polymer resin, and compounding the pre-pellet or the pre-pellet to which a polymer resin is further added to be pelletized.

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

Abstract: A display device includes a data driver having i data output terminals (i being a natural number greater than 1) and outputting data voltages to the i data output terminals in accordance with a source output enable signal provided from a timing controller, an output controller connected between the i data output terminals and i data lines, and i garbage switches respectively connected to the i data lines and connecting the i data lines to a ground terminal at a power input timing when a power supply voltage is applied to the display device, and interrupting the connection between the i data lines and the ground terminal at a timing later than an output timing of a first source output enable signal provided from the timing controller after the power input timing.