Abstract: A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may, be formed under a portion of the schottky junction.

Abstract: A high-voltage semiconductor device and a method of manufacturing the high-voltage semiconductor device are provided. For example, with the above device and method drift regions having first depths are formed in a semiconductor substrate by doping first impurities. The drift regions are spaced apart from each other to define a channel region between the drift regions. Source/drain regions having second depths are formed at first portions of the drift regions by doping second impurities. Impurity accumulation regions having third depths are formed at second portions of the drift region adjacent to the source/drain regions by doping third impurities. A gate insulation layer pattern is formed on the semiconductor substrate to partially expose the source/drain regions. A gate conductive layer pattern is formed on a portion of the gate insulation layer pattern where the channel region is positioned.

Abstract: An apparatus and method are provided for decoding data of first and second control channels in a mobile communication system providing multi-media services including voice and data services. The apparatus includes an input section for selectively outputting data stored in first and second control channel input sections which store data of the first and second control channels, respectively, a viterbi decoder core block for outputting a decoding result by decoding the data output from the input section, an output section for storing the decoding result output from the viterbi decoder core block in one of first and second control channel output sections, and a controller for setting a second control channel delay flag, which is a signal for delaying data decoding for the second control channel, as “on” in order to perform data decoding for the first control channel if decoding start signals of the first and second control channels are simultaneously input.

Abstract: A method and apparatus are provided for managing a buffer that can reduce a buffer size and a number of buffers required for a receiving stage of a mobile communication system using block interleaving. In a deinterleaving buffer configured as a plurality of sub-buffers in a receiving stage of a mobile communication system for performing Reed-Solomon (RS) decoding on frames received through a wireless network, input buffer addresses of the received frames to be input to the deinterleaving buffer, and output buffer addresses of RS-decoded frames to be output to a higher layer, are set to be cyclic by a management process. The frames input to the deinterleaving buffer are RS-decoded in a sub-buffer unit and the RS-decoded frames are output to the higher layer. Newly received frames are stored in input addresses having a same pattern with a last pattern of the output addresses in the deinterleaving buffer.

Abstract: A semiconductor device fabrication method includes the steps of forming a first insulation layer and a first semiconductor layer sequentially on a semiconductor substrate having a buried diffusion region therein. A second insulation layer is formed on the first semiconductor layer. The first insulation layer, the first semiconductor layer, and the second insulation layer are then patterned to create openings that expose the buried diffusion region. A third insulation layer is formed on respective side walls of the openings on the exposed portions of the first semiconductor layer, first insulation layer and second insulation layer that form the openings. A first epitaxial layer is formed on the semiconductor substrate exposed through the openings. A second epitaxial layer is then formed on the first epitaxial layer to be connected to the first semiconductor layer, thereby forming an active base region and a second conductive type collector region in the second epitaxial layer of the first and second openings.

Abstract: There is provided a viterbi decoder for decoding convolutional data. The convolutional data includes punctured data and non punctured data. The decoder includes a branch metric unit for calculating branch metrics of the received convolutional data. An add-compare-select unit selects current and next path selection information and calculates a current state metric and a next state metric of the punctured data, from the branch metrics and a previous state metric. A traceback unit traces the current and the next path selection information selected in the add-compare-select unit to find a maximum likelihood path from which the convolutional data was received, and outputs decoded data. A controller generates a plurality of decoding control signals to the branch metric unit, the add-compare-select unit, and the traceback unit.

Abstract: The present invention relates to an integrated viterbi decoder with improved test function. The viterbi decoder recovers original symbol and data bits from convolutional binary symbol stream, reducing a noise and data loss originated from a channel fading. For enhancing the test function of the viterbi decoder, the viterbi decoder of the present invention stores predetermined test control signals in a test register. During a test, the test control signals are synchronized with a test clock apart from a frame synchronous signal of the viterbi decoder. The test time of the viterbi decoder, thus, is not restricted by the frame synchronous signal. As a result, the test time of the viterbi decoder can be reduced without addition of an external pin.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film having one portion below a surface of the semiconductor substrate and the other portion on the semiconductor substrate in a second region to the same thickness as the insulating film, which improves an operation speed even at a low voltage.

Abstract: A semiconductor device fabrication method includes the steps of forming a first insulation layer and a first semiconductor layer sequentially on a semiconductor substrate having a buried diffusion region therein. A second insulation layer is formed on the first semiconductor layer. The first insulation layer, the first semiconductor layer, and the second insulation layer are then patterned to create openings that expose the buried diffusion region. A third insulation layer is formed on respective side walls of the openings on the exposed portions of the first semiconductor layer, first insulation layer and second insulation layer that form the openings. A first epitaxial layer is formed on the semiconductor substrate exposed through the openings. A second epitaxial layer is then formed on the first epitaxial layer to be connected to the first semiconductor layer, thereby forming an active base region and a second conductive type collector region in the second epitaxial layer of the first and second openings.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating film having one portion below a surface of the semiconductor substrate and the other portion above the surface of the semiconductor substrate a first region, and a semiconductor layer formed on the semiconductor substrate in a second region to the same thickness as the insulating film, which improves an operation speed even at a low voltage.

Abstract: A semiconductor device is disclosed, in which a capacitor lower electrode is formed of doped polysilicon and a capacitor upper electrode is formed of metal material to improve voltage coefficient characteristic. The semiconductor device includes a semiconductor substrate in which an active region and a field region are defined, a gate electrode and source and drain regions formed in the active region of the semiconductor substrate, a field oxide film formed in the field region of the semiconductor substrate, a capacitor lower electrode and a resistor formed of a doped polysilicon on the field oxide film, a capacitor dielectric film formed in a predetermined region on the capacitor lower electrode, and a capacitor upper electrode formed of metal material on the capacitor dielectric film.

Abstract: A semiconductor device is disclosed, in which a capacitor lower electrode is formed of doped polysilicon and a capacitor upper electrode is formed of metal material to improve voltage coefficient characteristic. The semiconductor device includes a semiconductor substrate in which an active region and a field region are defined, a gate electrode and source and drain regions formed in the active region of the semiconductor substrate, a field oxide film formed in the field region of the semiconductor substrate, a capacitor lower electrode and a resistor formed of a doped polysilicon on the field oxide film, a capacitor dielectric film formed in a predetermined region on the capacitor lower electrode, and a capacitor upper electrode formed of metal material on the capacitor dielectric film.

Abstract: A CMOS analog semiconductor apparatus and a fabrication method thereof are provided that are capable of selectively oxidizing a polysilicon to form a single layer having a conductive region and an insulation region of a semiconductor apparatus. The apparatus and method improve at least a step coverage problem of a semiconductor apparatus by using a simpler process. Further, the apparatus and method reduce a defective wiring and cracks to increase yield and reliability of the product. The apparatus can include a capacitor having a lower electrode formed on the field insulation layer of the semiconductor substrate, a first insulation layer formed on the field insulation layer including the lower electrode so as to expose a contact region for connecting with the lower electrode. An upper electrode is formed on an upper surface of the first insulation layer over the lower electrode except for the contact region. A resistance device is formed on the upper electrode.

Abstract: A method for fabricating a bipolar transistor improves the fast characteristics of the transistor at low operating voltages. An oxide film is formed on a semiconductor substrate, in which a buried layer is formed, and a floating poly base is formed on the oxide film. An insulating film is then formed on the entire surface of the semiconductor substrate including the floating poly base. The insulating film and the floating poly base are etched to define a base region and a collector region, and a first epitaxial layer is formed in the base and collector regions, with the first epitaxial layer having a smaller thickness than the oxide film. A second epitaxial layer is formed on the first epitaxial layer, and impurities are implanted into the second epitaxial layer in the base and collector regions. A second polysilicon layer is then formed on the second epitaxial layer in the base region, and electrodes are formed on the semiconductor surface.

Abstract: A method for fabricating a semiconductor device having a base electrode, an emitter electrode, and a collector electrode, includes the steps of: forming first, second, and buried layers in a semiconductor substrate; forming first, second, and third epitaxial layers using the respective buried layers as seeds; forming an isolation region between the first and second epitaxial layers; forming first, second, and third impurity regions connected to the respective buried layers through the respective epitaxial layers; forming fourth, fifth, and sixth impurity regions in the respective epitaxial layers; forming polysilicon layers on the respective epitaxial layers, respectively; defining first, second, and third emitter electrode regions as well as first, second, and third base contact regions; etching portions of the polysilicon layers excluding the emitter electrode regions and the base contact regions down to a predetermined depth; oxidizing the etched portions of the polysilicon layer to grow an oxide layer; im

Abstract: The method for forming a semiconductor device isolation layer, which advantageously simplifies the manufacture and planarization of the device, includes the steps of forming a V-shaped groove of a predetermined width and depth in a device isolation region of a semiconductor substrate and subjecting the substrate to a thermal oxidation process to form the device isolation layer.

Abstract: A bottom lead semiconductor chip stack package which includes a first body and a second body. The first body includes a pair of lead frames, each lead frame having a first lead portion and a second lead portion. A protrusion enclosed in a solder extends from the first lead portion. The first body also includes a semiconductor chip containing chip pads disposed on the surface thereof, the chip pads being connected to the solder enclosed protrusions. The second body has substantially the same structural configurations as the first body and is reversely stacked relative to the first body such that the semiconductor chips are disposed in opposing relationship relative to each other. An adhesive attaches the lead frames of the first body to the corresponding lead frames of the second body.

Abstract: A refrigerant expansion device for a refrigeration cycle comprises a housing, a passage formed penetrating the housing, an expansion means for expanding the refrigerant passing through the passage and a flow rate control means for bypassing some of the refrigerant passing through the expansion means according to the pressure of the refrigerant, for supplying to the low pressure portion of the passage, and for controlling the flow rate of the refrigerant through the expansion means.

Abstract: An improved CMOS analog semiconductor apparatus and a fabrication method thereof which are capable of selectively oxidizing a polysilicon, and forming a conductive region and an insulation region of a semiconductor apparatus, for thus improving a metal step coverage of the semiconductor apparatus by using a simpler process, so that it is possible to reduce a defective wiring and crack, and to increase a yield and reliability of the product.