Abstract: A flip chip-type nitride semiconductor light emitting diode includes a light transmittance substrate, an n-type nitride semiconductor layer, an active layer, a p-type nitride semiconductor layer and a mesh-type DBR reflecting layer. The mesh-type DBR reflecting layer has a plurality of open regions. The mesh-type DBR reflecting layer is composed of first and second nitride layers having different Al content. The first and second nitride layers are alternately stacked several times to form the mesh-type DBR reflecting layer. An ohmic contact layer is formed on the mesh-type DBR reflecting layer and on the p-type nitride semiconductor layer.

Abstract: Disclosed herein is a vertical type nitride semiconductor light emitting diode. The nitride semiconductor light emitting diode comprises an n-type nitride semiconductor layer, an active layer formed under the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed under the active layer, and an n-side electrode which comprises a bonding pad formed adjacent to an edge of an upper surface of the n-type nitride semiconductor layer and at least one extended electrode formed in a band from the bonding pad. The bonding pad of the n-side electrode is formed adjacent to the edge of the upper surface of the n-type nitride semiconductor layer acting as a light emitting surface, thereby preventing a wire from shielding light emitted from the active layer. The extended electrode can be formed in various shapes, and prevents concentration of current density, thereby ensuring effective distribution of the current density.

Abstract: Disclosed herein is a flip-chip type nitride semiconductor light emitting diode. The light emitting diode comprises an n-type nitride semiconductor layer formed on a transparent substrate and having a substantially rectangular upper surface, an n-side electrode which comprises at least one bonding pad adjacent to at least one corner of the upper surface of the n-type nitride semiconductor layer, extended electrodes formed in a band from the bonding pad along four sides of the upper surface of the n-type nitride semiconductor layer and one or more fingers extended in a diagonal direction of the upper surface from the bonding pad and/or the extended electrodes, an active layer and a p-type nitride semiconductor layer sequentially stacked on a region of the n-type nitride semiconductor layer where the n-side electrode is not formed, and a highly reflective ohmic contact layer formed on the p-type nitride semiconductor layer.

Abstract: Integrated circuit devices include a core block having a plurality of output ports and a plurality of input ports and a vector input terminal. The core block generates core internal data responsive to output data from the input ports and is configured to output the core internal data during scan testing and to selectively generate core output data for the output ports responsive to the core internal data or to test vector serial input data from the vector input terminal. An input side sub logic circuit unit generates sub data for the plurality of input ports responsive to data input to the first sub logic circuit unit. A multiplexer (MUX) unit between the core block and the first sub logic circuit unit selectively provides the sub data or the output data as inputs to the input ports of the core block responsive to a MUX control signal.

Abstract: A method of fabricating a vertical structure nitride semiconductor light emitting device having a cross-sectional shape of a polygon having five or more sides or a circle. A light emitting structure is formed on a sapphire substrate. A metal layer having a plurality of patterns is formed on the light emitting structure. The patterns of the metal layer each have a shape corresponding to a cross-sectional shape of a wanted final light emitting device and are spaced apart by a predetermined distance such that an upper surface of the light emitting structure is partially exposed. The light emitting structure is divided into a plurality of individualized light emitting structures by removing the light emitting structure below the exposed region between the patterns of the metal layer. The sapphire substrate is separated from the light emitting structure by irradiating a laser beam.

Abstract: Disclosed herein is a device for driving a LED for a flash of a camera, such as a digital camera or a camera of a mobile phone, which is capable of driving the LED in two modes to reduce power consumption. The LED drive device comprises the LED, a continuous low current driver for continuously supplying current which is lower than or equal to rated current of the LED to the LED, a high-current pulse driver for supplying current which is higher than the rated current of the LED to the LED for a predetermined period of time, and a mode selector for selecting one of the continuous low current driver and the high-current pulse driver to drive the LED. According to the present invention, it is possible to prevent unnecessary power consumption and deterioration of reliability of the LED, and obtain an image of brighter picture quality.

Abstract: Disclosed herein are a flip chip type nitride semiconductor light emitting device, which comprises a substrate for growing a nitride semiconductor material, an n-type nitride semiconductor layer formed on the substrate, an active layer formed on at least a part of the n-type nitride semiconductor layer, a p-type nitride semiconductor layer formed on the active layer, a bonding force providing layer formed on the p-type nitride semiconductor layer and adapted to provide a bonding force relative to the p-type nitride semiconductor layer, a reflective electrode layer formed on the bonding force providing layer, and adapted to reflect light produced in the active layer toward the substrate and to diffuse electric current, and a cap layer formed on the reflective electrode layer, and adapted to provide a bonding force between the reflective electrode layer and a bonding metal and to reduce contact resistance.

Abstract: An apparatus for testing an on-chip ROM and a method thereof are provided. By embedding the on-chip ROM test apparatus in a semiconductor chip and externally providing only minimal information, the apparatus and the method can prevent the possible exposure of ROM data stored in the ROM. Also, according to the apparatus and method, information related to the ROM address at which an error occurred can be provided together with the test result and by feeding the ROM address information back to the manufacturing process, product yield can be improved.

Abstract: A nitride semiconductor light-emitting device includes a first conductive nitride semiconductor layer; an active layer formed on the first conductive nitride semiconductor layer, and having at least one quantum well layer and at least one quantum barrier layer alternatively laminated; and a second conductive nitride semiconductor layer formed on the active layer, wherein at least one of the quantum well layer and quantum barrier layer in the active layer is doped with elemental Al in a concentration of less than 1%.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: An apparatus and a method for generating a modulation signal, for example, an eight-to-fourteen modulation (EFM) signal using a tangential push-pull (TPP) signal. The apparatus may include a TPP peak detector detecting peaks of the TPP signal; and a signal generator generating the modulation signal by determining the detected peaks of the TPP signal as edges of the modulation signal. The apparatus may determine peaks of a TPP signal as edges of a modulation signal to generate the modulation signal, thereby reducing or minimizing timing jitter caused by an asymmetry of marks or pits.

Abstract: In a nitride semiconductor LED, an n-doped nitride semiconductor layer is formed on a transparent substrate. An active layer is formed on the n-doped nitride semiconductor layer. A p-doped nitride semiconductor layer is formed on the active layer. A high reflectivity Ohmic contact layer of a mesh structure is formed on the p-doped nitride semiconductor layer and has a number of open areas for exposing the p-doped nitride semiconductor layer. A metal barrier layer is formed on at least a top region of the high reflectivity Ohmic contact layer. A p-bonding electrode is formed on the metal barrier layer. An n-electrode is formed on the n-doped nitride semiconductor layer.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: A data processing device having a central processing unit for fetching instructions from a program memory, decoding the instructions and sending a signal to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal; and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, and wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.

Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.

Abstract: Integrated circuit devices include a core block having a plurality of output ports and a plurality of input ports and a vector input terminal. The core block generates core internal data responsive to output data from the input ports. The core block is configured to output the core internal data during scan testing and to selectively generate core output data for the output ports responsive to the core internal data or to test vector serial input data from the vector input terminal. An input side sub logic circuit unit is configured for dynamic simulation testing and is coupled to the input ports of the core block. The input side sub logic circuit unit generates sub data for the plurality of input ports responsive to data input to the first sub logic circuit unit. A multiplexer (MUX) unit between the core block and the first sub logic circuit unit selectively provides the sub data or the output data as inputs to the input ports of the core block responsive to a MUX control signal.

Abstract: In an apparatus for testing an on-chip ROM and a method thereof, an on-chip ROM comprises a test control signal generator which, by using external test signals, including a test mode signal that sets the mode of the ROM to a test mode, a test clock signal which generates a clock used in testing the ROM, and a test reset signal for initialization, generates a ROM clock signal to operate the ROM and test control signals including a ROM address to access the ROM; a comparator which compares ROM data read from the ROM in response to the ROM address with external reference data; and a test result accumulator which, referring to the comparison result from the comparator, stores information related to whether an error exists, as a test result. If the comparison of the ROM data is performed to the last ROM address, the test result is externally output.

Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.

Abstract: A digital signal processing system performs different word-length arithmetic operations (e.g., 24-bit arithmetic and 16-bit arithmetic) using the same hardware. The digital signal processing system includes internal buses, a host processor coupled to the internal buses, a DSP coprocessor coupled to the internal buses for performing a digital signal processing under control of the host processor, and first and second data memories coupled to the internal buses. The DSP coprocessor further includes a random access memory (RAM) pointer for generating addresses to access the first and second data memories, a multiply and accumulate (MAC) unit for performing a multiply and accumulate operation, an arithmetic unit, a shift and exponent unit for shifting operands and for evaluating exponents, and a local decoder for decoding DSP commands from the host processor and controlling the RAM pointer, the arithmetic unit, and the shift and exponent unit.

Abstract: A microprocessor with an efficient and powerful coprocessor interface architecture is provided. The microprocessor has a set of generic coprocessor instructions on its instruction map and interface signals dedicated to the coprocessor interface. Depending on which coprocessor is interfaced to the microprocessor, the generic.coprocessor instructions are renamed to the specific coprocessor commands. When a coprocessor instruction for a specific function is fetched and decoded by the host processor, the appropriate command is issued through the coprocessor interface signals to the coprocessor and the coprocessor performs the required tasks. Hence, the coprocessor interfaced with the host processor need not have its own program. The pipelined operations of the coprocessor are synchronized with pipelined operations of the host processor.