Abstract: A microprocessor with an efficient and powerful coprocessor interface architecture is provided. The microprocessor has a set of generic coprocessor instructions on its instruction map and interface signals dedicated to the coprocessor interface. Depending on which coprocessor is interfaced to the microprocessor, the generic.coprocessor instructions are renamed to the specific coprocessor commands. When a coprocessor instruction for a specific function is fetched and decoded by the host processor, the appropriate command is issued through the coprocessor interface signals to the coprocessor and the coprocessor performs the required tasks. Hence, the coprocessor interfaced with the host processor need not have its own program. The pipelined operations of the coprocessor are synchronized with pipelined operations of the host processor.

Abstract: A data processing device comprising a central processing unit (CPU) for fetching instructions from a program memory, decoding the instructions and sending a signal (CCLK) to a coprocessor if a coprocessor type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal (CCLK); and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieve from the loop buffer for execution in a subsequent iteration of the loop, wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.

Abstract: Disclosed is a novel n-bit binary counter with low power consumption, which comprises a set of half-adders for adding a “1” to an n-bit input signal, which includes a lower-order m bit component and a higher-order (n−m) bit component, and a set of D (data) flip-flops for storing outputs of the half-adders. The set of half-adders are divided into two sections, one of which is a first adder section for adding a “1” to the lower-order m bit component and the other of which is a second adder section for adding a carry signal from the first adder section to the higher-order (n−m) bit component. The set of D flip-flops are divided into two sections, one of which is a first register section to store outputs of the first adder section and the other of which is a second register section to store outputs of the second adder section. The n-bit input signal is comprised of the outputs of the first and second register sections.