Abstract: In a nitride semiconductor LED, an n-doped nitride semiconductor layer is formed on a transparent substrate. An active layer is formed on the n-doped nitride semiconductor layer. A p-doped nitride semiconductor layer is formed on the active layer. A high reflectivity Ohmic contact layer of a mesh structure is formed on the p-doped nitride semiconductor layer and has a number of open areas for exposing the p-doped nitride semiconductor layer. A metal barrier layer is formed on at least a top region of the high reflectivity Ohmic contact layer. A p-bonding electrode is formed on the metal barrier layer. An n-electrode is formed on the n-doped nitride semiconductor layer.

Abstract: A digital data processor comprising a stack storage having a plurality of locations classified into two or more banks, and a stack pointer circuit pointing to one or more stack banks of the stack storage. The stack pointer circuit operates in response to decoding signals from an instruction decoder which decodes a current instruction to determine whether a one-word or a multi-word stack operation is desired.

Abstract: A data processing device having a central processing unit for fetching instructions from a program memory, decoding the instructions and sending a signal to a coprocessor if a coprocessor-type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal; and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieved from the loop buffer for execution in a subsequent iteration of the loop, and wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.

Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.

Abstract: An apparatus for searching for a cell and a method of acquiring a code unique to each cell in an asynchronous wideband Direct-Sequence Code Division Multiple Access (DS/CDMA) receiver, wherein the cell searching apparatus searches for a cell based on a received asynchronous wideband DS/CDMA signal in a receiver, the apparatus including a code group identifying unit for estimating and compensating for a frequency error between the synchronous channel and an internally generated primary synchronization code, estimating and compensating for channel degradation which the synchronous channel has experienced, and performing correlation on the compensated synchronous channel and available secondary synchronization codes, thereby identifying the code group; and a scrambling code identifying unit for performing correlation on a plurality of scrambling codes belonging to the code group, thereby obtaining a scrambling code unique to each cell.

Abstract: Described herein is a prepolymerized catalyst encapsulated with macromolecular monomers which is prepared by adding olefin mononers and diene compounds to a solid complex titanium catalyst for olefin polymerization and then polymerizing, and also relates to a method for polymerization or copolymerization capable of preparing polyolefins with high melt strength by polymerizing the olefin by using said catalyst.

Abstract: An apparatus for acquisition of an asynchronous wideband direct-sequence/code division multiple access signal, which acquires a long code from a direct-sequence/code division multiple access control channel signal, in which a common short code, and the long code are transmitted within one frame, and a group identification code indicating a code group, to which a base station belongs, are combined and transmitted with the common short code, includes: a long code masking correlation portion; a differentially coherent combining portion; a code group and frame timing acquisition portion; and a long code acquisition portion for acquiring the long code by correlating the long codes belonging to the acquired code group and the received long code, respectively.

Abstract: The present invention provides compositions comprising compounds having formula (I): 1

Abstract: Acquisition of initial code synchronization in a receiving system for a code division multiple access (CDMA) signal is realized by producing a complex digital signal having K components by sampling an analog signal derived from the received CDMA-modulated signal. Components of the complex digital signal are correlated with N code phases. The energies of these correlated values are examined, in parallel, to determine whether the ratio of the maximum energy within the block to the average energy in the block equals or exceeds a predetermined threshold. If so, this is a valid maximum, and the code synchronization is complete. If not, further components of the complex digital signal are correlated with another set of N code phases, and are examined in the same manner. Accordingly, reliable determination as to whether code synchronization has been achieved can be realized with minimal influence of channel distortion in a CDMA received signal.

Abstract: Integrated circuit devices include a core block having a plurality of output ports and a plurality of input ports and a vector input terminal. The core block generates core internal data responsive to output data from the input ports. The core block is configured to output the core internal data during scan testing and to selectively generate core output data for the output ports responsive to the core internal data or to test vector serial input data from the vector input terminal. An input side sub logic circuit unit is configured for dynamic simulation testing and is coupled to the input ports of the core block. The input side sub logic circuit unit generates sub data for the plurality of input ports responsive to data input to the first sub logic circuit unit. A multiplexer (MUX) unit between the core block and the first sub logic circuit unit selectively provides the sub data or the output data as inputs to the input ports of the core block responsive to a MUX control signal.

Abstract: The present invention provides a prepolymerized olefin polymerization catalyst and olefin polymerization method using the same. More particularly, the present invention provides a prepolymerized catalyst that is encapsulated with macromonomers produced by polymerizing olefin monomers with a vinyl-terminated polysiloxane compound in the presence of a solid titanium catalyst for olefin polymerization having been previously surface treated with silane compounds containing two or more vinyl groups, and a method for producing polyolefin having a high melt strength using the catalyst.

Abstract: Described herein is a prepolymerized catalyst encapsulated with macromolecular monomers which is prepared by adding olefin mononers and diene compounds to a solid complex titanium catalyst for olefin polymerization and then polymerizing, and also relates to a method for polymerization or copolymerization capable of preparing polyolefins with high melt strength by polymerizing the olefin by using said catalyst.

Abstract: In an apparatus for testing an on-chip ROM and a method thereof, an on-chip ROM comprises a test control signal generator which, by using external test signals, including a test mode signal that sets the mode of the ROM to a test mode, a test clock signal which generates a clock used in testing the ROM, and a test reset signal for initialization, generates a ROM clock signal to operate the ROM and test control signals including a ROM address to access the ROM; a comparator which compares ROM data read from the ROM in response to the ROM address with external reference data; and a test result accumulator which, referring to the comparison result from the comparator, stores information related to whether an error exists, as a test result. If the comparison of the ROM data is performed to the last ROM address, the test result is externally output.

Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.

Abstract: A digital signal processing system performs different word-length arithmetic operations (e.g., 24-bit arithmetic and 16-bit arithmetic) using the same hardware. The digital signal processing system includes internal buses, a host processor coupled to the internal buses, a DSP coprocessor coupled to the internal buses for performing a digital signal processing under control of the host processor, and first and second data memories coupled to the internal buses. The DSP coprocessor further includes a random access memory (RAM) pointer for generating addresses to access the first and second data memories, a multiply and accumulate (MAC) unit for performing a multiply and accumulate operation, an arithmetic unit, a shift and exponent unit for shifting operands and for evaluating exponents, and a local decoder for decoding DSP commands from the host processor and controlling the RAM pointer, the arithmetic unit, and the shift and exponent unit.

Abstract: A microprocessor with an efficient and powerful coprocessor interface architecture is provided. The microprocessor has a set of generic coprocessor instructions on its instruction map and interface signals dedicated to the coprocessor interface. Depending on which coprocessor is interfaced to the microprocessor, the generic.coprocessor instructions are renamed to the specific coprocessor commands. When a coprocessor instruction for a specific function is fetched and decoded by the host processor, the appropriate command is issued through the coprocessor interface signals to the coprocessor and the coprocessor performs the required tasks. Hence, the coprocessor interfaced with the host processor need not have its own program. The pipelined operations of the coprocessor are synchronized with pipelined operations of the host processor.

Abstract: A data processing device comprising a central processing unit (CPU) for fetching instructions from a program memory, decoding the instructions and sending a signal (CCLK) to a coprocessor if a coprocessor type instruction is decoded; a coprocessor for decoding the coprocessor-type instructions upon receipt of the signal (CCLK); and a loop buffer for receiving from the program memory instructions within a loop and storing the instructions within the loop when the coprocessor decodes a loop operation from the coprocessor-type instructions, wherein the instructions within the loop are retrieve from the loop buffer for execution in a subsequent iteration of the loop, wherein a disable signal is sent to the program memory for inhibiting access of the program memory while the instructions within the loop are retrieved from the loop buffer.

Abstract: A code division multiple access (CDMA) demodulating method and demodulator employing the demodulating method, the CDMA demodulating method including the steps of: (a) sequentially-storing all input data, which are over-sampled by M-fold and go through a number (N) of paths, in a predetermined first memory, where M and N are predetermined positive integers; (b) generating PN codes for each of the N paths and storing the PN codes in a predetermined second memory; (c) generating and sequentially-storing traffic walsh codes of one period, which correspond to a processing gain L, in a predetermined third memory; (d) multiplying a complex-conjugated value with one of the values stored in the first memory and one of the values stored in the second memory; (e) performing a control operation for storing the PN codes in a predetermined address of the second memory and a control operation for outputting data for each of the N paths from the first, second, and third memories; (f) multiplying the resultant value of the st

Abstract: Disclosed is a novel n-bit binary counter with low power consumption, which comprises a set of half-adders for adding a “1” to an n-bit input signal, which includes a lower-order m bit component and a higher-order (n−m) bit component, and a set of D (data) flip-flops for storing outputs of the half-adders. The set of half-adders are divided into two sections, one of which is a first adder section for adding a “1” to the lower-order m bit component and the other of which is a second adder section for adding a carry signal from the first adder section to the higher-order (n−m) bit component. The set of D flip-flops are divided into two sections, one of which is a first register section to store outputs of the first adder section and the other of which is a second register section to store outputs of the second adder section. The n-bit input signal is comprised of the outputs of the first and second register sections.