Abstract: An apparatus for searching for a cell and a method of acquiring a code unique to each cell in an asynchronous wideband Direct-Sequence Code Division Multiple Access (DS/CDMA) receiver, wherein the cell searching apparatus searches for a cell based on a received asynchronous wideband DS/CDMA signal in a receiver, the apparatus including a code group identifying unit for estimating and compensating for a frequency error between the synchronous channel and an internally generated primary synchronization code, estimating and compensating for channel degradation which the synchronous channel has experienced, and performing correlation on the compensated synchronous channel and available secondary synchronization codes, thereby identifying the code group; and a scrambling code identifying unit for performing correlation on a plurality of scrambling codes belonging to the code group, thereby obtaining a scrambling code unique to each cell.

Abstract: An apparatus for acquisition of an asynchronous wideband direct-sequence/code division multiple access signal, which acquires a long code from a direct-sequence/code division multiple access control channel signal, in which a common short code, and the long code are transmitted within one frame, and a group identification code indicating a code group, to which a base station belongs, are combined and transmitted with the common short code, includes: a long code masking correlation portion; a differentially coherent combining portion; a code group and frame timing acquisition portion; and a long code acquisition portion for acquiring the long code by correlating the long codes belonging to the acquired code group and the received long code, respectively.

Abstract: An apparatus for recovering timing using an equalizer of an E2PR4ML method and a method therefor and a last data judging apparatus. The timing recovery apparatus includes a sampling unit for sampling a reproduced signal and an equalizing unit for filtering the signal sampled by the sampling unit so as to output as a target signal E2PR4ML for detecting a timing error signal using the target signal output from the equalizing unit, phase synchronizing the detected timing error signal, and providing the phase-synchronized signal as a clock signal of the sampling unit.

Abstract: A digital timing recovery circuit for recovering a sampling clock of a playback signal in digital equipment, provides a fast phase obtaining time, reduces a phase error so as to generate a stable sampling clock and a dead zone effect caused by performing a quantization using a limited number of bits in hardware, and includes an analog-to-digital converter, a phase error detector, a phase error comparator, a loop filter, a reference voltage generator, a digital-to-analog converter and a variable voltage oscillator, to thereby reduce the phase obtaining time by varying the bandwidth of the loop filter according to the phase error size detected by the phase error detector and reduce a sampling phase error caused by noise at a constant state.