Abstract: Porous liners for through-glass vias and associated methods are disclosed. An example apparatus includes a glass layer having a through-hole. The example apparatus further includes a conductive material within the through-hole. The example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.

Abstract: Disclosed are an intermediate of edoxaban tosylate and a preparation method therefor, having the advantages that the preparation process is simple, reaction conditions are mild, the cost is low, and raw materials are easily to be obtained. The method comprises the synthesis steps of: substitution reaction, thiolation reaction, cyclization reaction, esterification reaction with alcohol to obtain a compound represented by formula (V), and then reacting to obtain a compound represented by formula (VI), or directly reacting the compound represented by formula (IV) under the effect of alcohol and acid, to obtain the compound represented by formula (VI), and subjecting the compound represented by formula (VI) to alkali hydrolysis and acid neutralization to obtain a compound represented by formula (VII).

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

Abstract: Microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. In one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second face, or the sidewall and extends from the surface into the glass core by a total depth of up to about 50 micron, the bulk region is a portion of the glass core further away from the surface than the surface region, and a density of the surface region is higher than a density of the bulk region, e.g., at least about 5% higher or at least about 7.5% higher.

Abstract: The present invention provides a huperzine B crystal and a preparation thereof. Specifically, the present invention provides a crystal form A of the huperzine B crystal. An X-ray diffraction pattern of the crystal form A has the following 2? angular characteristic absorption peak: 9.56±0.2, 13.90±0.2, 14.88±0.2, 16.00±0.2, 25.39±0.2, and 28.78±0.2.

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

Abstract: A continuous solid organic matter pyrolysis polygeneration system and method for using the system is disclosed. The pyrolysis polygeneration system mainly includes a processing system, a drying furnace, a pyrolysis furnace, a cooling furnace, a tail gas treatment system, and a gas treatment system and a protective gas circulation system cooperate with each other to realize the multi-level rational utilization of energy, and are suitable for the continuous and rapid pyrolysis and carbonization of various solid organic matter in the actual production. While realizing the polygeneration of coke, wood vinegar and tar, the maximum utilization of overall heat is realized through process optimization.

Abstract: The disclosure discloses a percussion and cutting composite drilling tool, which relates to the field of drilling equipment and is mainly used to solve the problems of low working efficiency and high wear rate of drill bit existed in breaking rocks only by cutting effect. The main structure comprises a PDC drill bit and a percussion drill bit, which is characterized by a percussion structure directly connected to the percussion drill bit. The disclosure provides a percussion and cutting composite drilling tool, which is suitable for strata under different geological conditions and has higher construction efficiency and lower bit wear.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate and a seed layer over the substrate. In an embodiment, sidewalls of the seed layer are sloped. In an embodiment, the electronic package further comprises a feature over the seed layer, where the feature is electrically conductive.

Abstract: A driving method and driving device for a display panel, and a display device. The driving method includes: in a first driving stage, controlling a data voltage signal input terminal to transmit a voltage corresponding to a data voltage to a gate of a drive transistor; and in a second driving stage, controlling the data voltage signal input terminal to transmit a hold voltage to a source of the drive transistor to couple the voltage of the gate of the drive transistor through the hold voltage of the source of the drive transistor.

Abstract: A method and device for driving a display panel and a display device. The method for driving a display panel includes: determining a brightness mode of the display panel, where the same display grayscale corresponds to different data voltages in different brightness modes; determining a data voltage characterization value according to the brightness mode, where the data voltage characterization value is used for characterizing a data voltage level in the brightness mode; determining a holding voltage corresponding to the data voltage characterization value according to the data voltage characterization value; and inputting, in a display holding frame of a current display image, the holding voltage to a source electrode of a drive transistor in each sub-pixel of the display panel.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a photonic die and at least one optical fiber. Devices and methods are shown that include an optical coupler and one or more correction regions to align a beam between the photonic die and the optical fiber.

Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a via opening through the core. In an embodiment, the via opening comprises sidewalls. In an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. In an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.

Abstract: The present disclosure generally relates to a method. The method may include providing a substrate and forming a seed layer on the substrate. The method may further include forming a first metal layer on selected portions of the seed layer to form exposed portions of the seed layer. The method may also include scanning a laser beam across the substrate to remove the exposed portions of the seed layer to form exposed portions of the substrate.

Abstract: A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.

Abstract: A continuous solid organic matter pyrolysis polygeneration system and method for using the system is disclosed. The pyrolysis polygeneration system mainly includes a processing system, a drying furnace, a pyrolysis furnace, a cooling furnace, a tail gas treatment system, and a gas treatment system and a protective gas circulation system cooperate with each other to realize the multi-level rational utilization of energy, and are suitable for the continuous and rapid pyrolysis and carbonization of various solid organic matter in the actual production. While realizing the polygeneration of coke, wood vinegar and tar, the maximum utilization of overall heat is realized through process optimization.

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.

Abstract: The present disclosure is directed to a carrier chuck having a base plate with a top surface, at least one electrode positioned in a first carrier region of the top surface and configured to produce an electrostatic force to retain a panel placed on the carrier chuck during panel processing, and a dielectric layer positioned over the at least one electrode. The at least one electrode extends from the top surface by a height of at least 20 um.