Patents by Inventor Yonggang Li

Yonggang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120087668
    Abstract: Embodiments of the present invention relate to the field of communications, and in particular, disclose a method and a device for generating and receiving an OOFDM signal, and a wavelength-division multiplexing system. The method for generating an OOFDM signal includes: converting a channel of serial high-speed data to N channels of parallel low-speed data; performing modulation mapping on the N channels of parallel low-speed data respectively to obtain N channels of information sequences; expanding the N channels of information sequences to 2N+2 channels of information sequences which have a Hermitian symmetric structure; performing inverse Fast Fourier Transform on the 2N+2 channels of information sequences, and then performing parallel-to-serial conversion to obtain an OFDM baseband signal; performing digital-to-analog conversion on the OFDM baseband signal to obtain an OFDM analog signal; and modulating the OFDM analog signal to an optical carrier to obtain an OOFDM signal.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Yonggang Li, Mingliang Deng, Jing Zhang, Kun Qiu, Lei Liu
  • Publication number: 20110123725
    Abstract: A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.
    Type: Application
    Filed: February 2, 2011
    Publication date: May 26, 2011
    Inventors: Omar J. Bchir, Houssam Jomaa, Islam A. Salama, Yonggang Li
  • Patent number: 7923059
    Abstract: A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate, covering sections of the first electrically conductive layer with a mask (410) such that the first electrically conductive layer has a masked portion and an unmasked portion, forming a second electrically conductive layer (710, 1210), the second electrically conductive layer forming only over the unmasked portion of the first electrically conductive layer, and removing the mask and the masked portion of the first electrically conductive layer. In an embodiment, the mask covering sections of the first electrically conductive layer is a non-electrically conductive substance (1010) applied with a stamp (1020). In an embodiment, the mask is a black oxide layer.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: April 12, 2011
    Assignee: Intel Corporation
    Inventors: Omar J. Bchir, Houssam Jomaa, Islam A. Salama, Yonggang Li
  • Publication number: 20110058340
    Abstract: A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 10, 2011
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy
  • Patent number: 7891091
    Abstract: A method of enabling selective area plating on a substrate (201) includes forming a first electrically conductive layer (310) on the substrate, covering the electrically conductive layer with an anti-electroless plating layer (410), patterning the substrate in order to form therein a feature (510, 520) extending through the anti-electroless plating layer and the first electrically conductive layer, forming a second electrically conductive layer (610) adjoining and electrically connected to the first electrically conductive layer, forming a third electrically conductive layer (710) over the second electrically conductive layer, and removing the anti-electroless plating layer and the first electrically conductive layer.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: February 22, 2011
    Inventors: Yonggang Li, Islam Salama
  • Publication number: 20100289154
    Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.
    Type: Application
    Filed: March 23, 2010
    Publication date: November 18, 2010
    Inventors: Yonggang Li, Amruthavalll P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
  • Patent number: 7749900
    Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 6, 2010
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
  • Publication number: 20100163295
    Abstract: In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. In this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Mihir Roy, Mahadevan Suryakumar, Yonggang Li
  • Publication number: 20100163535
    Abstract: A method of forming a pattern (700) on a work piece (1260) includes placing a pattern mask (1210) over the work piece, placing an aperture (100, 500, 600, 1220) over the pattern mask, and placing the work piece in a beam of electromagnetic radiation (1240). The aperture includes three adjacent sections. A first section (310) has a first side (311), a second side (312), and a first length (313). A second section (320) has a third side (321) adjacent to the second side, a fourth side (322), a second length (323), and a first width (324). A third section (330) has a fifth side (331) adjacent to the fourth side, a sixth side (332), and a third length (333). The first and third lengths are substantially equal. The first and third sections are complementary shapes, as defined herein.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: Yonggang Li, Islam Salama
  • Publication number: 20100126009
    Abstract: A method of enabling selective area plating on a substrate (201) includes forming a first electrically conductive layer (310) on the substrate, covering the electrically conductive layer with an anti-electroless plating layer (410), patterning the substrate in order to form therein a feature (510, 520) extending through the anti-electroless plating layer and the first electrically conductive layer, forming a second electrically conductive layer (610) adjoining and electrically connected to the first electrically conductive layer, forming a third electrically conductive layer (710) over the second electrically conductive layer, and removing the anti-electroless plating layer and the first electrically conductive layer.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 27, 2010
    Inventors: Yonggang Li, Islam Salama
  • Publication number: 20100101084
    Abstract: In some embodiments, same layer microelectronic circuit patterning using hybrid laser projection patterning (LPP) and semi-additive patterning (SAP) is presented. In this regard, a method is introduced including patterning a first density region of a laminated substrate surface using LPP, patterning a second density region of the laminated substrate surface using SAP, and plating the first and second density regions of the laminated substrate surface, wherein features spanning the first and second density regions are directly coupled. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 29, 2010
    Inventors: John Guzek, Yonggang Li
  • Publication number: 20100078805
    Abstract: A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Yonggang Li, Amruthavalli P. Alur, Devarajan Balaraman, Xiwang Qi, Charan K. Gurumurthy
  • Patent number: 7603883
    Abstract: An apparatus and method is disclosed for drawing continuous metallic wire having a first diameter to a metallic fiber having a reduced second diameter. A feed mechanism moves the wire at a first linear velocity. A laser beam heats a region of the wire to an elevated temperature. A draw mechanism draws the heated wire at a second and greater linear velocity for providing a drawn metallic fiber having the reduced second diameter.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: October 20, 2009
    Assignee: University of Central Florida
    Inventors: Nathaniel R. Quick, Aravinda Kar, Yonggang Li, Raymond R. McNeice
  • Publication number: 20090238516
    Abstract: Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Inventors: Omar J. Bchir, Islam Salama, Charan Gurumurthy, Houssam Jomaa, Ravi Nalla, Yonggang Li
  • Patent number: 7583871
    Abstract: Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: September 1, 2009
    Inventors: Omar J. Bchir, Islam Salama, Charan Gurumurthy, Houssam Jomaa, Ravi Nalla, Yonggang Li
  • Publication number: 20090170239
    Abstract: A method, comprises drilling a set of one or more microvias in a semiconductor package with an aperture, wherein drilling the set of microvias comprises to use an aperture that has a phase shift region to reduce a spot size of a drilling beam that is used to form the set of microvias.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventor: Yonggang Li
  • Publication number: 20090152743
    Abstract: A routing layer for a microelectronic device includes a first region (110, 510) containing a first trench (111, 511), a second region (120, 520) containing a second trench (121, 521), and an electrically conductive material (230, 530) in the first trench and in the second trench. The first trench has a first depth (115) and the second trench has a second depth (125) that is different from the first depth.
    Type: Application
    Filed: December 15, 2007
    Publication date: June 18, 2009
    Inventors: Houssam JOMAA, Islam A. SALAMA, Yonggang LI
  • Patent number: 7541463
    Abstract: The invention discloses novel sulfur-containing naphthalimide derivatives, and the preparation and uses thereof. The conjugated plane of naphthalimide derivatives of the invention is enlarged by incorporating 5-or 6-membered heteroaromatic ring and/or introducing S heteroatom, thus increasing the anti-tumor activity of naphthalimide. The compounds of the invention displays significant inhibiting activities to the proliferation of various tumor cells such as human lung cancer, gastric cancer, liver cancer, leucocythemia and the like. The inhibition of cell proliferation is dose-dependent.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: June 2, 2009
    Assignees: East China University of Science and Technology, Shanghai Institute of Materia Medica, Chinese Academy of Science, Dalian University of Technology
    Inventors: Xuhong Qian, Yonggang Li, Yufang Xu, Jian Ding, Liping Lin, Zehong Miao, Hong Zhu, Baoyuan Qu
  • Publication number: 20090111994
    Abstract: The present invention relates to a novel process for preparing losartan, an imidazole derivative with the chemical name 2-n-butyl-4-chloro-5-hydroxymethyl-1-{[2?-(1H-tetrazol-5-yl)biphenyl-4-]methyl}imidazole, and pharmacologically active salts thereof. The invention further relates to novel intermediates which are suitable for preparing losartan and to novel processes for preparing intermediate compounds which are suitable for preparing losartan. One aspect of the invention is a process for preparing a compound of the general formula I which can form as an intermediate in an inventive preparation of losartan.
    Type: Application
    Filed: February 2, 2006
    Publication date: April 30, 2009
    Applicant: RATIOPHARM GMBH
    Inventors: Yaping Wang, Yonggang Li, Yulin Li, Guojun Zheng, Yi Li
  • Publication number: 20090084755
    Abstract: A method for forming at least one micro-via on a substrate is disclosed. The method comprises drilling at least one hole in a substrate by using a first laser beam. The first laser beam has an energy distribution, which is more at edges of the first laser beam than at the center of the first laser beam. The method further comprises forming at least one blank pattern on a top surface of the substrate and around an outer periphery of the at least one hole by removing at least a portion of the substrate by using a second laser beam. At least one blank pattern of the plurality of blank pattern corresponds to pad of the at least one micro-via. Thereafter, the method comprises filling the plurality of blank patterns and the at least one micro-via with a conductive material to form at least micro-via.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Islam Salama, Yonggang Li