Abstract: A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

Abstract: A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

Abstract: A tray apparatus may include a housing, a tray slidably accommodated in the housing to be opened or closed, a rotary lock pivotally coupled to the housing at a hinge portion of the rotary lock and locking the tray to the housing when external shock is applied to the tray beyond a predetermined value, wherein a center of gravity of the rotary lock is positioned above the hinge portion, and a holding unit for holding the rotary lock in a normal state so that the rotary lock maintains an original position thereof.

Abstract: A semiconductor device includes a plurality of bank groups including at least two banks, respectively, and a plurality of address counters corresponding to the plurality of bank groups in a one-to-one manner. A refresh operation of a selected bank group is performed in response to a bank group refresh command.

Abstract: A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to a preamble signal, a pre-driver for generating a driving signal in response to the first and second control signals and the preamble signal, and an output buffer for driving an output pad in response to the driving signal.

Abstract: A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit.

Abstract: A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit.

Abstract: A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

Abstract: A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals.

Abstract: A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.

Abstract: Disclosed is a method of manufacturing the photoactive layer of organic photovoltaic cells using aerosol jet printing. The photoactive layer of the organic photovoltaic cell has high crystallinity and is easily formed into a multilayer structure, thus simplifying the process of manufacturing the organic photovoltaic cells. The solar power conversion efficiency of the organic photovoltaic cells including the photoactive layer is increased, thus facilitating the production of environmentally friendly energy.

Abstract: An anti-opening apparatus locks a tray so as to prevent the tray from opening when impact such as head impact is applied to a crash pad. In the tray anti-opening apparatus, the tray is mounted so as to be pulled into or out of a housing fixedly coupled to a crash pad. A rotary bar is hinged to the housing at an intermediate portion thereof, extends toward the tray on one side thereof, extends in a direction which crosses the extension direction of one side thereof on the other side thereof, and is rotated such that one side thereof approaches one surface of the tray when impact is applied to the crash pad. A pin is coupled on one side of the rotary bar, and a free end of the pin is inserted into an insertion hole formed in the tray when the rotary bar is rotated.

Abstract: A tray apparatus may include a housing, a tray slidably accommodated in the housing to be opened or closed, a rotary lock pivotally coupled to the housing at a hinge portion of the rotary lock and locking the tray to the housing when external shock is applied to the tray beyond a predetermined value, wherein a center of gravity of the rotary lock is positioned above the hinge portion, and a holding unit for holding the rotary lock in a normal state so that the rotary lock maintains an original position thereof.

Abstract: A data strobe signal generating circuit includes a pre-driver control unit for selectively transferring a ground voltage and a supply voltage, as a first control signal and a second control signal, in response to first and second clock pulse signals, wherein the second control signal is driven in response to a preamble signal, a pre-driver for generating a driving signal in response to the first and second control signals and the preamble signal, and an output buffer for driving an output pad in response to the driving signal.

Abstract: A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty control unit, a first DLL driver, a second DLL driver, a delay model, a phase comparator, and a shift control unit. In the DLL, a first duty control unit and a second duty control unit control each duty rate of the output clocks of a first and a second delay lines respectively through the EMRS input or the fuse option. Therefore, it is possible to control the duty rate of DLL clocks through the EMRS input or the fuse option.

Abstract: The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for next generation high-integration and high-frequency memory devices such as DDR2 SDRAMs.

Abstract: There is provided a circuit for generating an internal power voltage capable of stably controlling an internal power voltage before generating a reference voltage during an initial power-up operation of a semiconductor device. The circuit for generating an internal power voltage includes: an internal power reset controller for outputting a control signal in response to an activated reference signal and an external power voltage wherein the reference signal is activated after the external power voltage is inputted; and an internal power generator for generating the internal power voltage using the external power voltage in response to the activated reference signal wherein the internal power generator is disabled in response to the control signal.

Abstract: There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty control unit, a first DLL driver, a second DLL driver, a delay model, a phase comparator, and a shift control unit. In the DLL, a first duty control unit and a second duty control unit control each duty rate of the output clocks of a first and a second delay lines respectively through the EMRS input or the fuse option. Therefore, it is possible to control the duty rate of DLL clocks through the EMRS input or the fuse option.