Abstract: There is provided a DLL capable of controlling a duty rate of a clock by a fuse option or an EMRS input. The DLL includes a first clock buffer, a second clock buffer, a first delay line, a second delay line, a shift register, a first duty control unit, a second duty control unit, a first DLL driver, a second DLL driver, a delay model, a phase comparator, and a shift control unit. In the DLL, a first duty control unit and a second duty control unit control each duty rate of the output clocks of a first and a second delay lines respectively through the EMRS input or the fuse option. Therefore, it is possible to control the duty rate of DLL clocks through the EMRS input or the fuse option.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: A data output circuit of a memory device comprises an output enable signal generating unit, an output driving unit, an output driving unit and an output enable control unit. The output enable signal generating unit generates a reference output enable signal in response to a read command and outputting a plurality of output enable signals in response to a rising DLL clock and a falling DLL clock. The output driving unit drives data synchronously with respect to the rising DLL clock and the falling DLL clock in response to the output enable signals at a read mode. The output enable control unit disables the falling DLL clock when the output enable signals are all disabled. As a result, current consumption is reduced because the falling DLL clock is generated only when the output enable signal is generated.