Patents by Inventor Yong-Hwan Ryu

Yong-Hwan Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110111532
    Abstract: Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.
    Type: Application
    Filed: November 5, 2010
    Publication date: May 12, 2011
    Inventors: Yong-Hwan RYU, Jae-Seung HWANG, Sung-Un KWON, Kyoung-Ha EOM
  • Publication number: 20090011590
    Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
    Type: Application
    Filed: June 10, 2008
    Publication date: January 8, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Hwan RYU, Jun SEO, Eun-Young KANG, Jae-Seung HWANG, Sung-Un KWON
  • Publication number: 20070284692
    Abstract: The structure of the present invention comprises a semiconductor substrate and a trench region formed on the semiconductor substrate. The trench region includes an extended funnel portion in the vicinity of the semiconductor substrate surface. A device isolation layer is formed at the trench region. The device isolation layer includes a void formed at a lower level than the funnel portion. The sidewalls of the hard mask pattern and the internal walls of the trench region are etched to form a funnel portion with an extended trench region at the vicinity of the semiconductor substrate surface. Accordingly, the void in the trench region does not extend above a surface of the semiconductor substrate.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Woo Lee, Dae-Woong Kim, Yong-Hwan Ryu